公开(公告)号：US11221910B2

公开(公告)日：2022-01-11

申请号：US16516936

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: Methods, systems, and devices for media scrubber operations in a memory system are described. A controller may, for example, count a quantity of forwarded code words in a memory medium during a scrubbing period. The controller may add the quantity to a total quantity of forwarded code words in the memory medium. The controller may refrain from forwarding additional code words based on the quantity. The controller may write a valid logic state to a spare bit when the spare bit is assigned to an erroneous bit in a code word. A separate memory cell may indicate a change in spare bit assignments and whether spare bits include valid logic states. The controller may retrieve a code word from a memory medium and invert one or more bits of the code word before writing the code word to the memory medium.

公开(公告)号：US11119946B2

公开(公告)日：2021-09-14

申请号：US16414771

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/12 ,  G06F12/0804 ,  H03M13/27 ,  H03M13/00 ,  G06F12/0891

Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

公开(公告)号：US10990472B2

公开(公告)日：2021-04-27

申请号：US16516916

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C29/44 ,  G06F11/07 ,  G06F11/14 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G06F11/30 ,  G06F11/10 ,  G11C16/24 ,  G11C16/26

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

公开(公告)号：US10831653B2

公开(公告)日：2020-11-10

申请号：US16249817

申请日：2019-01-16

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C29/00 ,  G06F12/06 ,  G06F11/10

Abstract: Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a forwarded code word when the code word becomes unreliable or invalid close to or beyond an error recovery capability of the memory subsystem. The memory subsystem may configure the forwarded code word using a forwarded code word format and structure, which may include a bit field in the forwarded code word to indicate a code word condition and to store a quantity of duplicates of a forwarding address. When the memory subsystem receives a code word, the memory system may determine the code word as a forwarded code word such that the memory system may determine a forwarding address (e.g., from the code word). The memory subsystem may then use the forwarding address to access user data.

公开(公告)号：US20200034226A1

公开(公告)日：2020-01-30

申请号：US16516916

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G06F11/07 ,  G11C16/24 ,  G11C16/26

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

公开(公告)号：US20190147923A1

公开(公告)日：2019-05-16

申请号：US16171831

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C7/10 ,  G06F13/18 ,  H04L12/801

Abstract: Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.