公开(公告)号：US11461170B2

公开(公告)日：2022-10-04

申请号：US16993956

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  William A. Melton ,  Justin Eno

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0875

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

公开(公告)号：US11373714B2

公开(公告)日：2022-06-28

申请号：US16108077

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Justin Eno ,  Samuel E. Bradshaw

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/04 ,  G06F12/02 ,  G11C16/10

Abstract: A group of sectors of a memory is provisioned for a logical volume such that an unprovisioned capacity of the memory interleaves at least a subset of the group of sectors to provide proximity disturb isolation. A request to access the memory is received, the request including a logical address within the logical volume. A sector within the group of sectors is identified, the sector corresponding to the logical address, and the requested access is performed in the sector within the group of sectors.

公开(公告)号：US20220083252A1

公开(公告)日：2022-03-17

申请号：US17019843

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： Justin Eno ,  Sean S. Eilert

IPC: G06F3/06

Abstract: Methods, systems, and devices for indication-based avoidance of defective memory cells are described. A non-volatile memory component may store information regarding one or more memory cells of a volatile memory component that a host device for the volatile memory component is to avoid accessing. The one or more memory cells may be defective for example. The device may transmit, to the non-volatile memory component, a request for an indication of the one or more memory cells of the volatile memory component that the host device is to avoid accessing, and the non-volatile memory may transmit such an indication to the host device. The host device may refrain from writing or reading from the one or more memory cells of the volatile memory component.

公开(公告)号：US10810119B2

公开(公告)日：2020-10-20

申请号：US16138867

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Justin Eno ,  Samuel E. Bradshaw

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16 ,  G11C16/34

Abstract: A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.

公开(公告)号：US10795810B2

公开(公告)日：2020-10-06

申请号：US16127025

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin Eno

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06

Abstract: A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.

公开(公告)号：US10665322B2

公开(公告)日：2020-05-26

申请号：US15979308

申请日：2018-05-14

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin Eno

IPC: G06F11/00 ,  G11C29/00 ,  G11C29/44 ,  G06F12/02 ,  G06F11/10

Abstract: Remapping portions of a memory system having a plurality of non-volatile memory dice. A processing device performs a first error analysis of subslice elements to identify a first group of a predetermined number of subslice elements having highest error rates. The processing device determines which of the subslice elements are user subslice elements and remaps user subslice elements of the first group to spare subslice elements to remove subslice elements having the highest rates from a user space of the memory system. The processing device performs a second error analysis to identify a second group of subslice elements having the highest error rates and identifies user subslice elements of the first group that is/are not in the second group. For an identified user subslice element or elements of the first group not in the second group, the processing device reverses the remapping to reinstate removed subslice element(s) back into the user space.

公开(公告)号：US20200142792A1

公开(公告)日：2020-05-07

申请号：US16183628

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin Eno

IPC: G06F11/20 ,  G06F3/06

Abstract: A technique of receiving a write transaction directed to a group of memory parcels of a memory device from a client source. The technique determines a state of a first indicator used to indicate which one of two data structures contains a newer mapping of the group of memory parcels, while the other data structure contains an older mapping of the group of memory parcels. The technique determines a state of a second indicator used to indicate which one of the two data structures is in current use for the group of memory parcels and compares the states of the two indicators. When a data structure in current use does not contain the newer mapping, the technique changes the state of the second indicator to the state of the first indicator. The technique writes content of the write transaction to storage locations based on the newer mapping.