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公开(公告)号：US09589602B2
公开(公告)日：2017-03-07
申请号：US14836726
申请日：2015-08-26
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
CPC classification number: G11C7/22 , G11C7/065 , G11C7/1006 , G11C7/1012 , G11C7/106 , G11C7/12 , G11C8/10
Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.
Abstract translation: 本公开包括与在存储器中执行比较操作有关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储多个第一元件的第一组存储器单元，以及耦合到第二接入线路并被配置为存储多个第二元件的第二组存储器单元。 该装置可以包括：控制器，被配置为通过控制感测电路来执行多个操作而不经由输入/输出（I / O）线传输数据，使多个第一元件与多个第二元件进行比较， 可以并行地比较多个第一元件和多个第二元件。
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公开(公告)号：US20160266873A1
公开(公告)日：2016-09-15
申请号：US15063986
申请日：2016-03-08
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari , Kyle B. Wheeler
CPC classification number: G06F7/535 , G06F2207/535 , G11C7/06 , G11C7/10 , G11C7/1006 , G11C11/4076 , G11C11/4091
Abstract: Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include dividing the first vector by the second vector by performing a number of operations. The method can include performing at least one of the number of operations without transferring data via an input/output (I/O) line.
Abstract translation: 本公开的示例提供了用于在存储器中执行可变位长度分割操作的装置和方法。 一个示例性方法包括对包括代表多个分红的可变长度元素的第一向量执行可变长度除法运算，并存储在耦合到存储器阵列的第一存取线和多条感测线的存储器单元组中， 矢量包括表示存储在耦合到第二存取线的存储器单元组和存储器阵列的感测线的数目的存储器单元中的多个除数的可变长度元件。 该方法可以包括通过执行多个操作来将第一向量除以第二向量。 该方法可以包括执行多个操作中的至少一个，而不经由输入/输出（I / O）线传送数据。
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公开(公告)号：US11449266B2
公开(公告)日：2022-09-20
申请号：US17004135
申请日：2020-08-27
Applicant: Micron Technology, Inc.
Inventor： Adam J. Hieb , Adam C. Guy , Sanjay Tiwari , Todd A. Marquart
Abstract: A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.
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公开(公告)号：US10896042B2
公开(公告)日：2021-01-19
申请号：US16207786
申请日：2018-12-03
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
IPC: G06F9/30 , G06F7/60 , G06F15/78 , G11C11/4091 , G11C7/10
Abstract: Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.
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公开(公告)号：US20200227096A1
公开(公告)日：2020-07-16
申请号：US16835007
申请日：2020-03-30
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
IPC: G11C7/06 , G11C11/4091 , G11C7/10
Abstract: Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.
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Patent Agency Ranking
公开(公告)号：US10607665B2
公开(公告)日：2020-03-31
申请号：US15093448
申请日：2016-04-07
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
IPC: G06F12/00 , G11C7/06 , G11C11/4091 , G11C7/10
Abstract: Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.
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公开(公告)号：US20200004502A1
公开(公告)日：2020-01-02
申请号：US16564366
申请日：2019-09-09
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
IPC: G06F7/523 , G11C7/10 , G11C11/4096
Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.
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公开(公告)号：US10409557B2
公开(公告)日：2019-09-10
申请号：US15911668
申请日：2018-03-05
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
IPC: G06F7/535
Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.
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公开(公告)号：US20180203671A1
公开(公告)日：2018-07-19
申请号：US15911668
申请日：2018-03-05
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari
IPC: G06F7/535
CPC classification number: G06F7/535
Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.
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公开(公告)号：US09947376B2
公开(公告)日：2018-04-17
申请号：US15625543
申请日：2017-06-16
Applicant: Micron Technology, Inc.
Inventor： Sanjay Tiwari , Kyle B. Wheeler
CPC classification number: G11C7/065 , G11C7/1006 , G11C11/4091 , G11C19/28
Abstract: Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.
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