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公开(公告)号：US08898396B2
公开(公告)日：2014-11-25
申请号：US13453380
申请日：2012-04-23
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/879 , H04L12/933 , H04L12/861 , H04L12/935 , H04L12/947
CPC分类号： H04L49/15 , H04L49/109 , H04L49/252 , H04L49/3036 , H04L49/90 , H04L49/901
摘要： Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.
摘要翻译： 在芯片上的软件管道（“NOC”）中的内存共享，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过 存储器通信控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，包括将计算机软件应用程序分段成软件流水线的阶段， 所述软件流水线包括一个或多个执行路径; 在至少两个阶段中分配要共享的存储器，包括创建智能指针，所述智能指针包括用于确定何时可以释放所述共享存储器的数据元素; 根据用于确定何时可以释放共享存储器的数据元素确定可以释放共享存储器; 并释放共享内存。
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42.发明授权公开(公告)号：US08473667B2
公开(公告)日：2013-06-25
申请号：US11972753
申请日：2008-01-11
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F12/0808 , G06F12/0815
摘要： A network on chip (‘NOC’), and methods of operation of a NOC, that maintains cache coherency with invalidation messages, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including an invalidating module configured to send, to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory and the selected IP blocks, each selected IP block configured to invalidate the contents of the cached memory responsive to receiving the invalidation message.
摘要翻译： 一个片上网络（NOC），以及NOC的操作方法，通过无效消息来保持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器 IP块通过存储器通信控制器和网络接口控制器适配于路由器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括无效 模块，其被配置为向所选择的IP块发送无效消息，所述无效消息表示使缓存的存储器和所选择的IP块无效的指令，每个所选择的IP块被配置为响应于接收到所述无效消息而使所缓存的存储器的内容无效。
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公开(公告)号：US08020168B2
公开(公告)日：2011-09-13
申请号：US12117897
申请日：2008-05-09
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译： 一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于 下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。
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公开(公告)号：US20090282222A1
公开(公告)日：2009-11-12
申请号：US12117897
申请日：2008-05-09
IPC分类号： G06F9/30
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译： 一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于 下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。
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45.发明申请公开(公告)号：US20090182954A1
公开(公告)日：2009-07-16
申请号：US11972753
申请日：2008-01-11
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F12/0808 , G06F12/0815
摘要： A network on chip (‘NOC’), and methods of operation of a NOC, that maintains cache coherency with invalidation messages, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including an invalidating module configured to send, to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory and the selected IP blocks, each selected IP block configured to invalidate the contents of the cached memory responsive to receiving the invalidation message.
摘要翻译： 片上网络（“NOC”）和NOC的操作方法，其使得无效消息保持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器 IP块通过存储器通信控制器和网络接口控制器适配于路由器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括无效 模块，其被配置为向所选择的IP块发送无效消息，所述无效消息表示使缓存的存储器和所选择的IP块无效的指令，每个所选择的IP块被配置为响应于接收到所述无效消息而使所缓存的存储器的内容无效。
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公开(公告)号：US20090138567A1
公开(公告)日：2009-05-28
申请号：US12102038
申请日：2008-04-14
IPC分类号： G06F15/167
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译： 提供体现在机器可读介质中的设计结构。 该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器 通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及每个网络接口控制器通过路由器控制IP间块通信; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。
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47.发明授权External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit 有权外部辅助执行单元接口，用于从发布单元到片外辅助执行单元的指令格式转换公开(公告)号：US09075623B2
公开(公告)日：2015-07-07
申请号：US13352907
申请日：2012-01-18
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译： 在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地 处理核心中的其他功能单元。 外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。 通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于 连接多个不同的AXU设计。
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48.发明申请EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT 有权外部辅助执行单元接口切换辅助执行单元公开(公告)号：US20130185542A1
公开(公告)日：2013-07-18
申请号：US13352907
申请日：2012-01-18
IPC分类号： G06F9/30
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译： 在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地 处理核心中的其他功能单元。 外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。 通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于 连接多个不同的AXU设计。
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公开(公告)号：US08248401B2
公开(公告)日：2012-08-21
申请号：US12407297
申请日：2009-03-19
CPC分类号： G06T15/06 , G06T15/40 , G06T17/005
摘要： A circuit arrangement, program product and method utilize the known view orientation for an image frame to be rendered to optimize the generation and/or use of an Accelerated Data Structure (ADS) used in physical rendering-based image processing. In particular, it has been found that while geometry primitives that are not within a view orientation generally cannot be culled from a scene when a physical rendering technique such as ray tracing is performed, those primitives nonetheless have a smaller impact on the resulting image frame, and as a result, less processing resources can be applied to such primitives, leaving greater processing resources available for processing those primitives that are located within the view orientation, and thereby improving overall rendering performance.
摘要翻译： 电路布置，程序产品和方法利用已呈现的图像帧的已知视图方向来优化在基于物理渲染的图像处理中使用的加速数据结构（ADS）的生成和/或使用。 特别地，已经发现，当执行诸如光线跟踪的物理渲染技术时，不在视图方向内的几何图元通常不能从场景中被淘汰，但是这些图元对所得到的图像帧具有较小的影响， 并且因此，可以将更少的处理资源应用于这样的图元，留下更多的处理资源可用于处理位于视图方向内的那些图元，从而提高整体渲染性能。
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50.发明申请ROLLING TEXTURE CONTEXT DATA STRUCTURE FOR MAINTAINING TEXTURE DATA IN A MULTITHREADED IMAGE PROCESSING PIPELINE 失效在多路图像处理管道中维护纹理数据的滚动纹理语境数据结构公开(公告)号：US20110292063A1
公开(公告)日：2011-12-01
申请号：US12787110
申请日：2010-05-25
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.
摘要翻译： 多线程渲染软件流水线架构使用滚动纹理上下文数据结构来存储与在软件管线中处理的不同纹理相关联的多个纹理上下文。 每个纹理上下文存储特定纹理的状态数据，并且便于通过软件流水线中的多个并行级访问纹理数据。 此外，纹理上下文能够被“滚动”或被复制以实现需要用于特定纹理的不同状态数据的再现流水线的不同阶段以独立地彼此独立地访问纹理数据，并且不需要停止 管道，以确保管道的阶段之间共享纹理数据的同步。
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