公开(公告)号：US20220352202A1

公开(公告)日：2022-11-03

申请号：US17856703

申请日：2022-07-01

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11573 ,  H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  G11C8/14 ,  H01L21/67 ,  H01L27/11551 ,  H01L27/11521 ,  H01L21/02

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell stack structure surrounding a first channel structure and a second channel structure; a first source select line overlapping with a first region of the cell stack structure and surrounding the first channel structure; and a second source select line overlapping with a second region of the cell stack structure and surrounding the second channel structure. Each of the first source select line and the second source select line includes a first select gate layer overlapping with the cell stack structure, a second select gate layer disposed between the first select gate layer and the cell stack structure, and a third select gate layer disposed between the first select gate layer and the second select gate layer.

公开(公告)号：US20220189977A1

公开(公告)日：2022-06-16

申请号：US17352003

申请日：2021-06-18

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11529 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11565 ,  G11C7/18

摘要： There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

公开(公告)号：US20220130855A1

公开(公告)日：2022-04-28

申请号：US17241729

申请日：2021-04-27

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11534

摘要： A semiconductor device includes a first insulating layer, a first bonding pad in the first insulating layer, a second insulating layer in contact with the first insulating layer, and a second bonding pad in the second insulating layer. The first bonding pad includes a first conductive layer and a first barrier layer surrounding the first conductive layer, and the second bonding pad includes a second conductive layer and a second barrier layer surrounding the second conductive layer. The second barrier layer is in contact with the first conductive layer. The second conductive layer is spaced apart from the first conductive layer. The first conductive layer includes a metal material which is different from a metal material included in the second conductive layer. The first and second barrier layers each include at least one of titanium and tantalum.

公开(公告)号：US20220093637A1

公开(公告)日：2022-03-24

申请号：US17204416

申请日：2021-03-17

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/00

摘要： A memory device and a respective manufacturing method are set forth, wherein the memory device includes: a peripheral circuit layer including a plurality of conductive pads; a bonding structure disposed on the peripheral circuit layer; a cell stack structure disposed on the bonding structure, the cell stack structure including a plurality of gate conductive patterns; and a plurality of vertical gate contact structures respectively connecting the plurality of conductive pads and the plurality of gate conductive patterns while penetrating the bonding structure, wherein each of the plurality of gate conductive patterns includes a first horizontal part and a second horizontal part, which extend horizontally from a cell region to a contact region, and a third horizontal part connected to one end of the first horizontal part and one end of the second horizontal part, the third horizontal part being connected to a corresponding gate contact structure.

公开(公告)号：US20220093621A1

公开(公告)日：2022-03-24

申请号：US17208453

申请日：2021-03-22

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11524 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24

摘要： A semiconductor device is provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.

公开(公告)号：US20220077163A1

公开(公告)日：2022-03-10

申请号：US17527888

申请日：2021-11-16

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.

公开(公告)号：US20220068963A1

公开(公告)日：2022-03-03

申请号：US17193383

申请日：2021-03-05

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526 ,  G11C8/14 ,  G11C7/18 ,  H01L23/528

摘要： A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

公开(公告)号：US20220068885A1

公开(公告)日：2022-03-03

申请号：US17188429

申请日：2021-03-01

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L25/065 ,  H01L27/06 ,  G11C5/06 ,  G11C5/02 ,  H01L23/538

摘要： A semiconductor device includes: a substrate with a cell region and a chip guard region, the chip guard region surrounding the cell region; a first chip guard extending over the chip guard region in a first direction; a second chip guard extending over the chip guard region in the first direction, the second chip guard being spaced apart from the first chip guard; and a third chip guard extending over the chip guard region in a second direction, the second direction intersecting the first direction. The first chip guard includes a first end portion, the second chip guard includes a second end portion, and the third chip guard includes a third end portion that is disposed between the first end portion and the second end portion.

公开(公告)号：US20210366922A1

公开(公告)日：2021-11-25

申请号：US17391987

申请日：2021-08-02

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11556 ,  G11C5/02 ,  H01L27/11582

摘要： A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance.

公开(公告)号：US20210358944A1

公开(公告)日：2021-11-18

申请号：US17074062

申请日：2020-10-19

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18

摘要： There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor device includes: a first stack structure including interlayer insulating layers and first conductive patterns, which are alternately stacked; a second stack structure including a second conductive pattern overlapping with the first stack structure, and a third conductive pattern overlapping with the first stack structure with the second conductive pattern interposed between the first stack structure and the third conductive pattern, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; channel structures penetrating the first stack structure and the second stack structure; and a bit line overlapping with the first stack structure with the second stack structure interposed between the first stack structure and the bit line.