摘要:
A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
摘要:
A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.
摘要:
A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.
摘要:
A processor is disclosed having a fetch unit that initiating interrupt service routines in redundant, unsynchronized threads. A counter is provided to track the difference between leading and trailing threads in terms of the number of instructions committed by the instruction execution circuitry. When the processor receives an external interrupt signal, the instruction fetch unit stalls the leading thread until the counter indicates that the threads are synchronized, and then simultaneously initiates an interrupt service routine in each of the threads. In a second embodiment similar to the first, the instruction fetch unit does not stall the leading thread, but rather, immediately initiates the interrupt service routine in the leading thread, and copies the difference to an interrupt counter. When the counter reaches zero, the fetch unit initiates the interrupt service routine in the trailing thread.