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    WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
    42.
    发明申请
    WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY 审中-公开

    公开(公告)号：US20200371918A1

    公开(公告)日：2020-11-26

    申请号：US16874516

    申请日：2020-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

    IPC: G06F12/0811 ,  G06F12/0815 ,  G06F3/06 ,  G06F9/38 ,  G06F12/126

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

    Method for Forming Constant Extensions in the Same Execute Packet in a VLIW Processor
    45.
    发明申请
    Method for Forming Constant Extensions in the Same Execute Packet in a VLIW Processor 审中-公开

    公开(公告)号：US20200310807A1

    公开(公告)日：2020-10-01

    申请号：US16846686

    申请日：2020-04-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

    IPC: G06F9/30 ,  G06F9/38

    Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

    Two-Dimensioanl Zero Padding in a Stream of Matrix Elements
    46.
    发明申请
    Two-Dimensioanl Zero Padding in a Stream of Matrix Elements 审中-公开

    公开(公告)号：US20190278596A1

    公开(公告)日：2019-09-12

    申请号：US16420457

    申请日：2019-05-23

    Applicant: Texas Instruments Incorporated

    Inventor： William Franklin Leven ,  Asheesh Bhardwaj ,  Son Hung Tran ,  Timothy David Anderson

    IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

    One-Dimensional Zero Padding in a Stream of Matrix Elements
    47.
    发明申请
    One-Dimensional Zero Padding in a Stream of Matrix Elements 审中-公开

    公开(公告)号：US20190278595A1

    公开(公告)日：2019-09-12

    申请号：US16420447

    申请日：2019-05-23

    Applicant: Texas Instruments Incorporated

    Inventor： Son Hung Tran ,  Shyam Jagannathan ,  Timothy David Anderson

    IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for a selected dimension of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When the selected dimension in the stream of vectors exceeds the specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

    CONTROLLING THE NUMBER OF POWERED VECTOR LANES VIA A REGISTER FIELD
    49.
    发明申请
    CONTROLLING THE NUMBER OF POWERED VECTOR LANES VIA A REGISTER FIELD 审中-公开

    公开(公告)号：US20170308141A1

    公开(公告)日：2017-10-26

    申请号：US15638407

    申请日：2017-06-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David Anderson ,  Duc Quang Bui

    IPC: G06F1/28 ,  G06F13/26 ,  G06F9/30

    Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

    Method to Extend the Number of Constant Bits Embedded in an Instruction Set
    50.
    发明申请
    Method to Extend the Number of Constant Bits Embedded in an Instruction Set 审中-公开
    扩展嵌入在指令集中的常数位数的方法

    公开(公告)号：US20150019845A1

    公开(公告)日：2015-01-15

    申请号：US14326969

    申请日：2014-07-09

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

    IPC: G06F9/30

    CPC classification number: G06F9/3853 ,  G06F9/30167

    Abstract: The invention allows a processor to maintain a fixed instruction width regardless of the width of the constants needed. The constant extension solves the problem of having variable length opcodes to accommodate longer constants. The invention allows the architecture to have a fixed width, regardless of the width of the constants specified, which simplify instruction decoding. Constant widths can be variable and extend beyond the fixed processor instruction width.

    Abstract translation: 本发明允许处理器维持固定的指令宽度，而与所需常数的宽度无关。 常数扩展解决了具有可变长度操作码以适应更长常数的问题。 本发明允许架构具有固定的宽度，而不管指定的常数的宽度，这简化了指令解码。 恒定宽度可以是可变的并且延伸超出固定的处理器指令宽度。

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