公开(公告)号：US10930769B2

公开(公告)日：2021-02-23

申请号：US16200691

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/94 ,  H01L29/51 ,  H01L29/78

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

公开(公告)号：US10283414B2

公开(公告)日：2019-05-07

申请号：US15628345

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Chih-Sheng Chang ,  Cheng-Hsien Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

公开(公告)号：US10276697B1

公开(公告)日：2019-04-30

申请号：US15795610

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L49/02 ,  H01L21/02 ,  H01L29/51 ,  H01L27/11585

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.