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41.发明申请INSTRUCTION EXECUTION UNIT THAT BROADCASTS DATA VALUES AT DIFFERENT LEVELS OF GRANULARITY 有权指定执行单位在不同级别的范围内广播数据值公开(公告)号：US20130339664A1
公开(公告)日：2013-12-19
申请号：US13976003
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3887
摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The first data structure is four times as large as the second data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second instruction to create a second replication data structure.
摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，用于在执行第一指令时存储要复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 第一个数据结构是第二个数据结构的四倍。 执行单元还包括复制逻辑电路，以在执行第一指令以创建第一复制数据结构时复制第一数据结构，并且在执行第二指令以创建第二复制数据结构时复制第二数据结构。
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公开(公告)号：US20130290672A1
公开(公告)日：2013-10-31
申请号：US13976435
申请日：2011-12-23
IPC分类号： G06F15/80
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F15/8092
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
摘要翻译： 描述了具有指令执行逻辑电路的装置。 指令执行逻辑电路具有输入向量元素路由电路，以对三个不同的指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素从多个 可用于输出输出向量元素的输入向量元素位置。 输出向量元素和每个输入向量元素位置是三个不同指令的三个可用位宽之一。 该装置还包括耦合到输入向量元素路由电路以屏蔽由输入向量路由选择元件电路产生的数据结构的掩蔽层电路。 掩蔽层电路被设计为以与三个可用位宽对应的三个不同的粒度级别进行掩蔽。
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43.发明申请Packed Data Rearrangement Control Indexes Generation Processors, Methods, Systems and Instructions 有权封装数据重排控制索引生成处理器，方法，系统和指令公开(公告)号：US20130283018A1
公开(公告)日：2013-10-24
申请号：US13977217
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收打包数据重排控制索引生成指令。 打包数据重排控制索引生成指令表示目的地存储位置。 响应于打包数据重排控制索引生成指令，将结果存储在目的地存储位置中。 结果包括代表压缩数据重排控制指标的至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US20130275730A1
公开(公告)日：2013-10-17
申请号：US13976998
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F9/30145
摘要： An apparatus is described that includes instruction execution logic circuitry to execute first, second, third and fourth instructions. Both the first instruction and the second instruction select a first group of input vector elements from one of multiple first non overlapping sections of respective first and second input vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups of the first and third instructions at a first granularity, where, respective resultants produced therewith are respective resultants of the first and third instructions. The masking circuitry is also to mask the first and second groups of the second and fourth instructions at a second granularity, where, respective resultants produced therewith are respective resultants of the second and fourth instructions.
摘要翻译： 描述了包括执行第一，第二，第三和第四指令的指令执行逻辑电路的装置。 第一指令和第二指令都从相应的第一和第二输入向量的多个第一非重叠部分之一中选择第一组输入向量元素。 第一组具有第一位宽度。 多个第一非重叠部分中的每一个具有与第一组相同的位宽度。 第三指令和第四指令都从相应的第三和第四输入向量的多个第二非重叠部分之一中选择第二组输入向量元素。 第二组具有比第一位宽大的第二位宽度。 多个第二非重叠部分中的每一个具有与第二组相同的位宽度。 该装置包括掩蔽层电路，以第一粒度掩蔽第一和第三指令的第一和第二组，其中由其产生的相应结果是第一和第三指令的相应结果。 掩蔽电路还以第二粒度掩蔽第二和第四指令的第一和第二组，其中由其产生的相应结果是第二和第四指令的相应结果。
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45.发明申请Packed Data Rearrangement Control Indexes Precursors Generation Processors, Methods, Systems, and Instructions 有权封装数据重排控制索引前驱生成处理器，方法，系统和说明公开(公告)号：US20130275729A1
公开(公告)日：2013-10-17
申请号：US13977356
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括结果，包括至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US10564966B2
公开(公告)日：2020-02-18
申请号：US13977171
申请日：2011-12-22
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed Vall , Mark J. Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed Vall , Mark J. Charney
IPC分类号： G06F9/30
摘要： A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask, indicates a shift count number of bits, and indicates a destination. The method further includes storing a result in the destination in response to the packed data operation mask shift instruction. The result includes a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits. Other methods, apparatus, systems, and instructions are disclosed.
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公开(公告)号：US20170192780A1
公开(公告)日：2017-07-06
申请号：US14984078
申请日：2015-12-30
申请人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
发明人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30192
摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.
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公开(公告)号：US09619226B2
公开(公告)日：2017-04-11
申请号：US13992230
申请日：2011-12-23
申请人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
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49.发明授权Instruction execution that broadcasts and masks data values at different levels of granularity 有权指令执行，以不同的粒度级别广播和屏蔽数据值公开(公告)号：US09424327B2
公开(公告)日：2016-08-23
申请号：US13976433
申请日：2011-12-23
CPC分类号： G06F21/6227 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/3802 , G06F17/30575 , G06F21/6254 , G06F21/70
摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.
摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，以在执行第一指令时存储待复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 当执行第一指令以创建第一复制数据结构时，执行单元还包括复制第一数据结构的复制逻辑电路，以及在执行第二数据指令以创建第二复制数据结构时复制第二数据结构。 执行单元还包括掩蔽逻辑电路，以第一粒度掩蔽第一复制数据结构，并以第二粒度掩蔽第二复制数据结构。 第二粒度是第一粒度的两倍。
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50.发明授权Instruction execution unit that broadcasts data values at different levels of granularity 有权指令执行单元，以不同的粒度级别广播数据值公开(公告)号：US09336000B2
公开(公告)日：2016-05-10
申请号：US13976003
申请日：2011-12-23
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3887
摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The first data structure is four times as large as the second data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second instruction to create a second replication data structure.
摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，用于在执行第一指令时存储要复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 第一个数据结构是第二个数据结构的四倍。 执行单元还包括复制逻辑电路，以在执行第一指令以创建第一复制数据结构时复制第一数据结构，并且在执行第二指令以创建第二复制数据结构时复制第二数据结构。
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