公开(公告)号：US20110003473A1

公开(公告)日：2011-01-06

申请号：US12881806

申请日：2010-09-14

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849

摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

摘要翻译： 提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。 此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

公开(公告)号：US07863186B2

公开(公告)日：2011-01-04

申请号：US12334746

申请日：2008-12-15

申请人： Wai-Kin Li ,  Haining Yang

发明人： Wai-Kin Li ,  Haining Yang

IPC分类号： H01L21/44

CPC分类号： H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

摘要： Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

摘要翻译： 通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。 然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。 退火步骤将多晶硅转化为硅化物。 由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。 使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

公开(公告)号：US07772119B2

公开(公告)日：2010-08-10

申请号：US12186923

申请日：2008-08-06

申请人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

公开(公告)号：US07709960B2

公开(公告)日：2010-05-04

申请号：US12186932

申请日：2008-08-06

申请人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L23/52

CPC分类号： H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。 高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。 每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

公开(公告)号：US07592247B2

公开(公告)日：2009-09-22

申请号：US11538550

申请日：2006-10-04

申请人： Haining Yang ,  Jack A. Mandelman ,  Wai-Kin Li

发明人： Haining Yang ,  Jack A. Mandelman ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  B82Y10/00 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1104

摘要： The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.

摘要翻译： 本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构 从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接 其间没有任何金属接触。 可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

公开(公告)号：US20090200674A1

公开(公告)日：2009-08-13

申请号：US12027448

申请日：2008-02-07

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal.

摘要翻译： 描述了形成用于连接线路的两个后端（BEOL）金属布线层的导电通孔的结构和方法。 该方法包括在第一介电层中形成具有第一尺寸宽度的第一互连结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻所述第二介电层中的互连沟槽; 通过使用光刻胶掩模蚀刻互连以形成过渡通孔的第一部分; 使光致抗蚀剂反应至少在横向上扩展光致抗蚀剂; 使用反应的光致抗蚀剂蚀刻所述介电层以形成过渡通孔的第二部分; 以及用金属填充所述互连沟槽和所述互连通孔。

公开(公告)号：US07569434B2

公开(公告)日：2009-08-04

申请号：US11335763

申请日：2006-01-19

申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L29/66742 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

摘要： In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了在衬底上制造PFET的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成具有第一厚度的PFET的栅极沟道区; 和（2）在衬底上形成具有大于第一厚度的第二厚度的PFET的至少一个复合源极/漏极扩散区域。 至少一个复合源极/漏极扩散区域适于在栅极沟道区域引起应变。 此外，显着地所有的至少一个复合源极/漏极扩散区域在PFET的栅极的底表面之下。 提供了许多其他方面。

公开(公告)号：US07560382B2

公开(公告)日：2009-07-14

申请号：US11467712

申请日：2006-08-28

申请人： Haining Yang ,  Thomas W. Dyer

发明人： Haining Yang ,  Thomas W. Dyer

IPC分类号： H01L21/44

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11

摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

摘要翻译： 本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构 并且将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。 导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

公开(公告)号：US07531384B2

公开(公告)日：2009-05-12

申请号：US11548298

申请日：2006-10-11

申请人： Chih-Chao Yang ,  Mukta Ghate Farooq ,  Keith Kwong Hon Wong ,  Haining Yang

发明人： Chih-Chao Yang ,  Mukta Ghate Farooq ,  Keith Kwong Hon Wong ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.

摘要翻译： 本发明提供了一种在封盖层/电介质层/扩散阻挡界面处具有改进的机械强度的半导体互连结构。 互连结构具有嵌入Cu封盖材料中的Cu扩散阻挡材料。 阻挡层可以部分地嵌入盖层中或完全嵌入封盖层中。

公开(公告)号：US20080290519A1

公开(公告)日：2008-11-27

申请号：US12186932

申请日：2008-08-06

申请人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L23/48

CPC分类号： H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.