公开(公告)号：US20240347444A1

公开(公告)日：2024-10-17

申请号：US18135319

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： PIN-JHU LI ,  SHIH-FAN KUAN

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76883 ,  H01L28/87 ,  H01L28/91

摘要： A conductive structure and a capacitor structure and a method of manufacturing a conductive structure are provided. The conductive structure includes a first support layer, a second support layer, a first conductive via, a third support layer and a second conductive via. The second support layer is disposed over the first support layer. The first conductive via is disposed between the first support layer and the second support layer. The third support layer is disposed over the second support layer. The second conductive via is disposed between the second support layer and the third support layer, and electrically connected to the first conductive via. A lateral surface of the first conductive via is discontinuous with a lateral surface of the second conductive via.

公开(公告)号：US12119226B2

公开(公告)日：2024-10-15

申请号：US17451967

申请日：2021-10-22

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Yexiao Yu ,  Zhongming Liu ,  Jia Fang

IPC分类号： H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/0332 ,  H01L21/02115 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76883

摘要： A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

公开(公告)号：US12087832B2

公开(公告)日：2024-09-10

申请号：US17303002

申请日：2021-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Chih Hsiung ,  I-Hung Li ,  Yi-Ruei Jhan ,  Yuan-Tien Tu

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L29/41775 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/5221 ,  H01L23/5283 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/12 ,  H01L27/0886

摘要： A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.

公开(公告)号：US20240290718A1

公开(公告)日：2024-08-29

申请号：US18656969

申请日：2024-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shao-Kuan LEE ,  Cheng-Chin LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC分类号： H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226

摘要： An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line, a first dielectric layer including a potion between the first metal line and the second metal line, and a first etching stop layer on the potion of the first dielectric layer.
A bottom surface of the first etching stop layer is level to a top surface of the first metal line and a top surface of the second metal line. The interconnect structure also includes a second etching stop layer including a first portion extending along the top surface of the second metal line, a second portion extending along a first sidewall of the first etching stop layer, and a third portion extending along a top surface of the first etching stop layer. The interconnect structure also includes a via on the first metal line.

公开(公告)号：US12057492B2

公开(公告)日：2024-08-06

申请号：US18367292

申请日：2023-09-12

申请人： Intel Corporation

发明人： Tahir Ghani ,  Byron Ho ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC分类号： H10N70/00 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H10B63/00 ,  H10N70/20 ,  H01L23/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20240222191A1

公开(公告)日：2024-07-04

申请号：US18089773

申请日：2022-12-28

申请人： Winbond Electronics Corp.

发明人： Ping-Lung YU ,  Po-Chun SHAO ,  Chu-Chun HSIEH

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76859 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/53266

摘要： A method for forming a semiconductor structure includes providing a substrate with an opening in or on the substrate. The method further includes conformally forming a barrier layer in the opening and on the substrate and performing an implantation process to implant a dopant into the barrier layer. The method further includes conformally forming a capping layer on the barrier layer and performing an annealing process, such that the dopant diffuses into the grain boundary of the barrier layer. The method further includes removing the capping layer and filling the opening with a conductive material.

公开(公告)号：US20240213152A1

公开(公告)日：2024-06-27

申请号：US17795117

申请日：2022-06-10

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Tieh-Chiang Wu ,  Lingxin Zhu

IPC分类号： H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC分类号： H01L23/528 ,  H01L21/76883 ,  H10B12/482

摘要： A semiconductor structure and a preparation method making it are disclosed. The semiconductor structure includes: a substrate, a bit line contact structure, a first epitaxial layer, a bit line and a second epitaxial layer. The structure includes bit line contact holes. The bit line contact structure is disposed in one of the bit line contact holes. The first epitaxial layer is epitaxially grown on the sidewalls of the bit line contact structure. The bit line includes a connection layer connected to the bit line contact structure. The second epitaxial layer is epitaxially grown on the sidewalls of the connection layer. The present disclosure can reduce the contact resistance and parasitic capacitance between the bit line contact structures and the bit lines, thereby improving the electrical performance of the semiconductor structure, thereby raising the reliability and yield of the semiconductor structure.

公开(公告)号：US20240213034A1

公开(公告)日：2024-06-27

申请号：US18601433

申请日：2024-03-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Chung-Ju Lee ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tien-I Bao ,  Tsai-Sheng Gau

IPC分类号： H01L21/321 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/3212 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2221/1063

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on the first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US20240194587A1

公开(公告)日：2024-06-13

申请号：US18079440

申请日：2022-12-12

申请人： International Business Machines Corporation

发明人： Koichi Motoyama ,  Oscar van der Straten ,  Chih-Chao Yang

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76883 ,  H01L23/53252 ,  H01L23/53266

摘要： Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.

公开(公告)号：US20240162332A1

公开(公告)日：2024-05-16

申请号：US18416508

申请日：2024-01-18

申请人： Intel Corporation

发明人： Subhash M. JOSHI ,  Jeffrey S. LEIB ,  Michael L. HATTENDORF

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L29/665

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.