公开(公告)号：US20110093575A1

公开(公告)日：2011-04-21

申请号：US12581280

申请日：2009-10-19

申请人： Shawn Joel Dube ,  Timothy M. Lambert

发明人： Shawn Joel Dube ,  Timothy M. Lambert

IPC分类号： G06F15/173 ,  G06F15/16

CPC分类号： G06F15/16

摘要： An information handling system (IHS) includes a processing system operating as a controller. A network interface controller is coupled to the processing system and receives communications from a remote administrator via a management network. An external virtual device link is coupled to the processing system.

摘要翻译： 信息处理系统（IHS）包括作为控制器操作的处理系统。 网络接口控制器耦合到处理系统并经由管理网络从远程管理员接收通信。 外部虚拟设备链路耦合到处理系统。

公开(公告)号：US20100306763A1

公开(公告)日：2010-12-02

申请号：US12472894

申请日：2009-05-27

申请人： Timothy M. Lambert ,  Kareem S. Seddik

发明人： Timothy M. Lambert ,  Kareem S. Seddik

IPC分类号： G06F9/455

CPC分类号： G06F9/45533 ,  G06F2009/45579 ,  G06F2009/45591

摘要： A system and method for providing dynamic access through which I/O access such as serial ports, and thus administrators who manage servers, can see, obtain health, state or interact concurrently with multiple VMs on a given physical server. More specifically, in certain embodiments, the system and method includes a dynamic port count virtual serial concentrator coupled with a virtualization device to map emulated serial ports to virtual machines along with a remote plugin that provide dynamic concurrent serial access to many virtual machine serial consoles under a secure and collaborative friendly environment.

摘要翻译： 用于提供动态访问的系统和方法，通过这些访问，I / O访问（如串行端口）以及管理服务器的管理员可以在给定的物理服务器上与多个虚拟机同时查看，获取运行状况或状态。 更具体地说，在某些实施例中，系统和方法包括与虚拟化设备耦合的动态端口计数虚拟串行集中器，以将仿真的串行端口映射到虚拟机以及向许多虚拟机串行控制台提供动态并发串行访问的远程插件 一个安全和协作友好的环境。

公开(公告)号：US07707534B2

公开(公告)日：2010-04-27

申请号：US11782743

申请日：2007-07-25

申请人： Timothy M. Lambert ,  Bianca Roxana Tudosa

发明人： Timothy M. Lambert ,  Bianca Roxana Tudosa

IPC分类号： G06F17/50

CPC分类号： G06Q10/06 ,  G06F17/5068 ,  G06Q10/10

摘要： A design tool for printed circuit boards displays a graphical representation of a printed circuit board layout through a graphical user interface (GUI). Comments for particular components of the printed circuit board layout can be entered through the graphical user interface. The comments are stored in a data file associated with the printed circuit board layout. Comments can be entered and viewed by multiple users in real time. Comments can be displayed through the graphical user interface in proximity to the component associated with the comment, thereby improving the efficiency with which designers can review and implement suggested changes to the PCB layout.

摘要翻译： 印刷电路板的设计工具通过图形用户界面（GUI）显示印刷电路板布局的图形表示。 可以通过图形用户界面输入印刷电路板布局的特定组件的注释。 注释存储在与印刷电路板布局相关联的数据文件中。 评论可以由多个用户实时输入和查看。 注释可以通过图形用户界面显示在与注释相关联的组件附近，从而提高设计人员可以查看和实现对PCB布局的建议更改的效率。

公开(公告)号：US20100058091A1

公开(公告)日：2010-03-04

申请号：US12200020

申请日：2008-08-28

申请人： Timothy M. Lambert ,  Jaydev Reddy ,  Ashish Munjal

发明人： Timothy M. Lambert ,  Jaydev Reddy ,  Ashish Munjal

IPC分类号： G06F1/28

CPC分类号： G06F1/263

摘要： An information handling system having plural processing modules, such as an information handling system blade chassis having plural information handling system blades, allocates power by determining an actual load sharing power loss associated with plural power supplies and applying the actual load sharing power loss to determine how much power to allocate to the information handling system modules. A chassis manager determines actual load sharing power loss by retrieving power information from plural power supplies. The actual load sharing power loss replaces a worst-case load sharing power loss assumed value to increase the amount power available for allocation to the information handling system modules.

摘要翻译： 具有多个处理模块的信息处理系统，例如具有多个信息处理系统叶片的信息处理系统叶片机箱，通过确定与多个电源相关联的实际负载分担功率损耗并应用实际负载分担功率损耗来分配功率，以确定如何 分配给信息处理系统模块的大量功能。 机箱管理器通过从多个电源中检索功率信息来确定实际的负载分担功率损耗。 实际的负载分担功率损耗取代了最差情况下的负载分担功率损耗假定值，以增加可用于分配给信息处理系统模块的功率。

公开(公告)号：US07483313B2

公开(公告)日：2009-01-27

申请号：US11669792

申请日：2007-01-31

申请人： Timothy M. Lambert ,  Shawn J. Dube

发明人： Timothy M. Lambert ,  Shawn J. Dube

IPC分类号： G11C7/00

CPC分类号： G11C16/06 ,  G11C7/1075

摘要： A device comprising a first port, a second port, and a non-volatile memory. The first port is coupled to and accessible by a first module, and the second port is coupled to and accessible by a second module. The non-volatile memory of the device comprises a first memory portion and a second memory portion. The first memory portion is writable by the first port and write protected from the second port, and the second memory portion is writable by the second port and write protected from the first port.

摘要翻译： 一种包括第一端口，第二端口和非易失性存储器的设备。 第一端口被耦合到第一模块并且可由第一模块访问，并且第二端口耦合到第二模块并且可由第二模块访问。 设备的非易失性存储器包括第一存储器部分和第二存储器部分。 第一存储器部分可由第一端口写入，并且从第二端口写保护，并且第二存储器部分可由第二端口写入，并且从第一端口写保护。

公开(公告)号：US20080183974A1

公开(公告)日：2008-07-31

申请号：US11669792

申请日：2007-01-31

申请人： Timothy M. Lambert ,  Shawn J. Dube

发明人： Timothy M. Lambert ,  Shawn J. Dube

IPC分类号： G06F12/00

CPC分类号： G11C16/06 ,  G11C7/1075

摘要： A device comprising a first port, a second port, and a non-volatile memory. The first port is coupled to and accessible by a first module, and the second port is coupled to and accessible by a second module. The non-volatile memory of the device comprises a first memory portion and a second memory portion. The first memory portion is writable by the first port and write protected from the second port, and the second memory portion is writable by the second port and write protected from the first port.

摘要翻译： 一种包括第一端口，第二端口和非易失性存储器的设备。 第一端口被耦合到第一模块并且可由第一模块访问，并且第二端口耦合到第二模块并且可由第二模块访问。 设备的非易失性存储器包括第一存储器部分和第二存储器部分。 第一存储器部分可由第一端口写入，并且从第二端口写保护，并且第二存储器部分可由第二端口写入，并且从第一端口写保护。

公开(公告)号：US08528046B2

公开(公告)日：2013-09-03

申请号：US12762671

申请日：2010-04-19

申请人： Timothy M. Lambert ,  Mukund P. Khatri

发明人： Timothy M. Lambert ,  Mukund P. Khatri

IPC分类号： G06F21/00

CPC分类号： G06F21/572 ,  G06F11/2284 ,  G06F12/1408 ,  G06F21/575 ,  G06F21/72 ,  G06F21/78 ,  H04L9/30

摘要： An information handling system includes a host mapped general purpose input output (GPIO), a shared memory, a board management controller, and a cryptography engine. The host mapped GPIO includes a plurality of registers. The board management controller is in communication with the host mapped GPIO and with the shared memory, and is configured to control accessibility to the plurality of registers in the GPIO, and to control write accessibility of the shared memory based on a private key received from a basic input output system requesting accessibility to the plurality of registers and write accessibility of the shared memory. The cryptography engine is in communication with the board memory controller, and is configured to authenticate the private key received from the board management controller.

公开(公告)号：US08499178B2

公开(公告)日：2013-07-30

申请号：US13361342

申请日：2012-01-30

申请人： Timothy M. Lambert ,  Jaydev Reddy ,  Ashish Munjal

发明人： Timothy M. Lambert ,  Jaydev Reddy ,  Ashish Munjal

IPC分类号： G06F1/00

CPC分类号： G06F1/263

摘要： An information handling system having plural processing modules, such as an information handling system blade chassis having plural information handling system blades, allocates power by determining an actual load sharing power loss associated with plural power supplies and applying the actual load sharing power loss to determine how much power to allocate to the information handling system modules. A chassis manager determines actual load sharing power loss by retrieving power information from plural power supplies. The actual load sharing power loss replaces a worst-case load sharing power loss assumed value to increase the amount power available for allocation to the information handling system modules.

摘要翻译： 具有多个处理模块的信息处理系统，例如具有多个信息处理系统叶片的信息处理系统叶片机箱，通过确定与多个电源相关联的实际负载分担功率损耗并应用实际负载分担功率损耗来分配功率，以确定如何 分配给信息处理系统模块的大量功能。 机箱管理器通过从多个电源中检索功率信息来确定实际的负载分担功率损耗。 实际的负载分担功率损耗取代了最差情况下的负载分担功率损耗假定值，以增加可用于分配给信息处理系统模块的功率。

公开(公告)号：US20120151097A1

公开(公告)日：2012-06-14

申请号：US12964465

申请日：2010-12-09

申请人： Timothy M. Lambert ,  Indrani Paul

发明人： Timothy M. Lambert ,  Indrani Paul

IPC分类号： G06F13/00

CPC分类号： G06F3/0689 ,  G06F3/0605 ,  G06F3/0632 ,  G06F3/067

摘要： An information handling system includes a backplane, a storage drive, and a board management controller. The board management controller is configured to discover a physical drive status of the drive from a storage enclosure processor, to receive a logical drive status of the drive, to read a backplane bay identification for the drive from a peripheral connector interface express extender or serial attached small computer system interface chipset logical drive number, and to construct a routing table for the drive to map the logical drive status with the physical drive status of the drive.

摘要翻译： 信息处理系统包括背板，存储驱动器和板管理控制器。 板管理控制器被配置为从存储机箱处理器发现驱动器的物理驱动器状态，以接收驱动器的逻辑驱动器状态，从外围连接器接口快速扩展器或串行连接读取驱动器的背板托架标识 小型计算机系统接口芯片组逻辑驱动器号，并构建一个路由表，使驱动器将逻辑驱动器状态与驱动器的物理驱动器状态进行映射。

公开(公告)号：US07840726B2

公开(公告)日：2010-11-23

申请号：US11403035

申请日：2006-04-12

申请人： Jon M. McGary ,  Brian L. Brelsford ,  Timothy M. Lambert

发明人： Jon M. McGary ,  Brian L. Brelsford ,  Timothy M. Lambert

IPC分类号： G06F5/00

CPC分类号： G06F13/4291

摘要： A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified, the data line is only changed at the GPIO in those instances in which the next succeeding data bit in the bit sequences is different from the preceding data bit. In those situations in which the next following bit sequence is not different, the clock line is triggered without the necessity of testing, and changing the logic level of the data line.

摘要翻译： 公开了一种用于编程现场可编程门阵列的系统和方法。 该系统涉及通过通用输入输出设备识别要发送到FPGA的下一个后续位序列。 一旦比特序列被识别，在比特序列中下一个后续数据比特与先前数据比特不同的那些实例中，数据线仅在GPIO处改变。 在下一个后续位序列不同的情况下，时钟线被触发而不需要测试，并且改变数据线的逻辑电平。