公开(公告)号：US5227321A

公开(公告)日：1993-07-13

申请号：US899830

申请日：1992-06-15

申请人： Ruojia Lee ,  Ceredig Roberts ,  Dave Cheffings

发明人： Ruojia Lee ,  Ceredig Roberts ,  Dave Cheffings

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/66575 ,  H01L21/266 ,  H01L21/823807 ,  H01L27/0928 ,  Y10S148/082 ,  Y10S148/143

摘要： A method for implanting diffusion regions during production of MOS transistors involves first patterning and etching a gate to produce a resist overhang covering at least one edge of the gate. Primary dopant is then implanted in the substrate to produce a first diffusion region having at least one boundary partially defined by the resist overhang covering the gate. By isotropically etching the resist on the gate, the gate itself is used as a mask during subsequent implantation of a halo diffusion region. The size of both the first diffusion region and the halo diffusion region is subsequently adjusted by annealing.

摘要翻译： 在制造MOS晶体管期间注入扩散区域的方法包括首先构图和蚀刻栅极以产生覆盖栅极的至少一个边缘的抗蚀剂突出端。 然后将主掺杂剂注入到衬底中以产生具有至少一个由覆盖栅极的抗蚀剂悬垂部分限定的边界的第一扩散区域。 通过对栅极上的抗蚀剂进行各向同性蚀刻，栅极本身在随后的晕圈扩散区域的注入期间用作掩模。 随后通过退火调整第一扩散区和卤素扩散区的尺寸。

公开(公告)号：US5219778A

公开(公告)日：1993-06-15

申请号：US800803

申请日：1991-11-27

申请人： Charles H. Dennison ,  Ruojia Lee ,  Yauh-Ching Liu ,  Pierre Fazan

发明人： Charles H. Dennison ,  Ruojia Lee ,  Yauh-Ching Liu ,  Pierre Fazan

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40

摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.

摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构组成，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。

公开(公告)号：US5208176A

公开(公告)日：1993-05-04

申请号：US603528

申请日：1990-10-25

申请人： Aftab Ahmad ,  Pierre C. Fazan ,  Ruojia Lee

发明人： Aftab Ahmad ,  Pierre C. Fazan ,  Ruojia Lee

IPC分类号： H01L21/308 ,  H01L21/32 ,  H01L21/334

CPC分类号： H01L29/66181 ,  H01L21/3081 ,  H01L21/32 ,  Y10S438/964

摘要： A DRAM cell having a doped monocrystalline silicon substrate for the cell's lower capacitor plate whose surface has been texturized multiple times to enhance cell capacitance. After texturization, a thin silicon nitride layer is deposited on top of the texturized substrate, followed by the deposition of a poly layer, which functions as the cell's upper, or field, capacitor plate. The nitride layer, conformal and thin compared to the surface texture of the mono substrate, transfers the texture of the substrate to the cell plate layer. The effective capacitor plate area is substantially augmented, resulting in a cell capacitance increase of at least approximately fifty percent compared to a conventional planar cell utilizing identical wafer area. The substrate is texturized by texturizing a thin polycrystalline silicon (poly) starter layer that has been deposited on top of the substrate by using an anisotropic etch or wet oxidation step, and then allowing the poly starter layer to be consumed, transferring the texture created on the poly starter layer to the underlying substrate. By subjecting the starter layer to either an etch or an oxidation step, atoms at the grain boundaries of the starter layer react more rapidly, thus establishing the texturization pattern. Once established, the starter layer's texturization pattern is transferred to the monocrystalline silicon surface by either etching or oxidizing the starter layer. Performing this texturization process multiple times produces greater texturization due to the consumption of the successive poly starter layers along their respective, uniquely superimposed grain boundaries.

摘要翻译： 具有用于电池的下电容器板的掺杂单晶硅衬底的DRAM单元，其表面已被多次构造以增强单元电容。 在纹理化之后，将薄的氮化硅层沉积在纹理化衬底的顶部上，随后沉积多层，其用作电池的上部或场域电容器板。 与单基板的表面纹理相比，保形和薄的氮化物层将基板的纹理转移到单元板层。 与使用相同晶片面积的常规平面单元相比，有效电容器板面积基本上增加，导致电池电容增加至少约百分之五十。 通过使用各向异性蚀刻或湿氧化步骤，已经沉积在衬底的顶部上的薄多晶硅（多晶）起始层进行纹理化，然后允许多晶硅起始层被消耗，转移在 多晶硅起始层到底层基板。 通过使起始层进行蚀刻或氧化步骤，起始层的晶界处的原子反应更快，从而建立了纹理化模式。 一旦建立，起始层的纹理化图案通过蚀刻或氧化起始层被转移到单晶硅表面。 由于沿着它们各自的独特叠加的晶界而消耗连续的多晶硅起始层，多次进行这种纹理化过程会产生更大的纹理化。

公开(公告)号：US5149665A

公开(公告)日：1992-09-22

申请号：US727702

申请日：1991-07-10

申请人： Ruojia Lee

发明人： Ruojia Lee

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Disclosed is a process and structure for use with a Flash E.sup.2 PROM and EPROM. The inventive structure allows for positioning of the control gates over the active area in a manner which allows for more error in the process thereby increasing yields. The inventive structure has transistor diffusion areas which are self-aligned with the floating and control gates and avoids both a field oxide etch and a buried N

摘要翻译： 公开了一种与Flash E2PROM和EPROM一起使用的过程和结构。 本发明的结构允许以有助于在过程中产生更多误差从而提高产量的方式在有效区域上定位控制栅极。 本发明的结构具有晶体管扩散区域，其与浮动栅极和控制栅极自对准，并避免场氧化物蚀刻和掩埋N

公开(公告)号：US5077225A

公开(公告)日：1991-12-31

申请号：US693731

申请日：1991-04-30

申请人： Ruojia Lee

发明人： Ruojia Lee

IPC分类号： H01L21/02

CPC分类号： H01L28/40 ,  Y10S438/911

摘要： A process for fabricating a stacked capacitor for use in monolithic integrated circuits using oxygen implantation. This invention provides a relatively simple process for manufacturing stacked capacitors having two series of interleaved plates. The process is unique, in that rather than requiring the use of a different material for each series of conductive plates, utilizes polycrystalline silicon for both series. The process proceeds with the deposition of alternating dielectric and polycrystalline silicon ("poly") layers, beginning and ending with a dielectric layer. Each poly layer is masked with photoresist, implanted with oxygen in unmasked regions, and then thermally annealed to convert all silicon in the unmasked regions into silicon dioxide. Each non-implanted poly region is horizontally offset from the non-implanted poly regions of the nearest superjacent and subjacent poly layers, which are, themselves, horizontally aligned. The resulting layer stack is masked and anisotropically etched, stopping on the bottom dielectric layer, to form a block of stacked layers, one vertical side of which comprises unoxidized edges of even numbered poly layers and oxidized edges of odd numbered poly layers, and a second vertical side of which comprises unoxidized edges of odd numbered poly layers and oxidized edges of even numbered poly layers. A tying layer is then blanket deposited over the block, masked and etched so that the unoxidized edges of even numbered poly layers are electrically connected by one a first typing layer remnant, while the oxidized edges of odd numbered poly layers are electrically connected by a second tying layer remnant.

摘要翻译： 一种制造用于使用氧注入的单片集成电路中的层叠电容器的方法。 本发明提供了一种用于制造具有两系列交错板的叠层电容器的相对简单的方法。 该方法是独特的，因为不是要求为每个系列的导电板使用不同的材料，而是为两个系列使用多晶硅。 该过程将以介电层开始和结束的交替电介质和多晶硅（“poly”）层的沉积进行。 每个多晶硅层被光刻胶掩蔽，在未掩模的区域中注入氧，然后热退火以将未掩模区域中的所有硅转化为二氧化硅。 每个未植入的多晶硅区域与最近的上层和下层多层的未注入的多晶区水平偏移，它们本身水平对准。 所得到的层堆叠被掩蔽并各向异性蚀刻，停止在底部介电层上，以形成堆叠层的块，其一个垂直侧包括偶数多层的未氧化边缘和奇数多层的氧化边缘，第二 其垂直侧包括奇数多层的未氧化边缘和偶数多层的氧化边缘。 然后将粘合层铺展在块上，被掩蔽和蚀刻，使得偶数多层的未氧化边缘通过一个第一分层层残留物电连接，而奇数多层的氧化边缘被电连接到第二层 捆扎层残余。