公开(公告)号：US6165863A

公开(公告)日：2000-12-26

申请号：US102331

申请日：1998-06-22

申请人： Ruojia Lee ,  Ralph Kauffman ,  J. Dennis Keller

发明人： Ruojia Lee ,  Ralph Kauffman ,  J. Dennis Keller

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10888 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/10811 ,  H01L28/91

摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

公开(公告)号：US5371701A

公开(公告)日：1994-12-06

申请号：US223477

申请日：1994-04-05

申请人： Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre Fazan ,  Steven D. Cummings

发明人： Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre Fazan ,  Steven D. Cummings

IPC分类号： H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10817

摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠三角形电池（SDC）电容器。 SDC由具有倒三角形横截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。

公开(公告)号：US5240796A

公开(公告)日：1993-08-31

申请号：US727834

申请日：1991-07-09

申请人： Ruojia Lee ,  J. Brett Rolfson

发明人： Ruojia Lee ,  J. Brett Rolfson

IPC分类号： G03F1/34

CPC分类号： G03F1/34

摘要： A method of fabricating a chromeless phase shift reticle. The method includes the steps of: depositing a layer of material on a transparent substrate to a thickness of "t"; patterning and anisotropically etching the material to form a pattern of openings to the substrate; depositing a phase shifter material over the layer of material and into the openings; polishing by chemical mechanical planarization (CMP) the phase shifter material; and selectively wet etching the initially deposited layer of material. This process forms a chromeless phase shift reticle having a pattern of phase shifters of a thickness of "t" with a pattern of light transmissive areas on the substrate therebetween. The thickness "t" and a phase shifter material index of refraction may be selected to achieve a 180.degree. phase shift between light transmitted through a phase shifter relative to light transmitted through a light transmissive area on the substrate.

摘要翻译： 一种制造无铬相移掩模版的方法。 该方法包括以下步骤：在透明衬底上沉积厚度为“t”的材料层; 图案化和各向异性地蚀刻材料以形成到基板的开口图案; 在所述材料层上沉积移相器材料并进入所述开口中; 通过化学机械平面化（CMP）抛光移相器材料; 并选择性地湿蚀刻初始沉积的材料层。 该过程形成具有厚度为“t”的移相器图案的无铬相移掩模版，并且其上的基板上具有透光区域的图案。 可以选择厚度“t”和移相器材料折射率来实现透射通过移相器的光相对于透射通过衬底上的透光区域的光的180度相移。

公开(公告)号：US5126290A

公开(公告)日：1992-06-30

申请号：US760026

申请日：1991-09-11

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/525

CPC分类号： H01L27/11206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory. With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

摘要翻译： 本发明提供了一种用于可编程只读存储器（PROM）的可编程结构，该可编程只读存储器利用在数字线上构造的单面臭氧间隔作为一次可编程节点。 氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的接口，具有单面臭氧间隔物，并且在可编程只读存储器中覆盖字线的平行列。 通过在行/列矩阵中的每个字线下方通过的每个数字线形成，从而提供可编程数字/字线矩阵。 矩阵中的数字和字线的每个交叉点将通过在相关联的数字/字线导体之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或零。

公开(公告)号：US5122848A

公开(公告)日：1992-06-16

申请号：US682623

申请日：1991-04-08

申请人： Ruojia Lee ,  Fernando Gonzalez

发明人： Ruojia Lee ,  Fernando Gonzalez

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L27/10864 ,  H01L29/66666 ,  H01L29/7827

摘要： An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portion of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

摘要翻译： 绝缘栅垂直FET具有在P型半导体衬底中沿着沟槽的侧壁形成的沟道区和栅极结构。 FET的漏极和源极区域形成在沟槽的台面和基部中。 可以从半导体衬底的顶表面制造到栅极，漏极和源极区域的所有接触。 沟槽的一个或多个侧壁用薄的栅极氧化物介电层氧化，随后是薄的多晶硅沉积膜以形成绝缘的栅极层。 反应离子蚀刻步骤从绝缘栅极层和沟槽的基底部分去除绝缘栅极层。 增强的N型注入器在沟槽的台面和基部中产生漏极和源极区域。 沟槽部分地填充有间隔氧化物层以减少栅极到源极重叠电容。 在绝缘栅极层上沉积保形导电多晶硅层。 导电多晶硅层的一部分在沟槽的表面上延伸到台面上以形成栅极接触。 场氧化物覆盖FET的整个表面，其在台面中打开以形成栅极和漏极接触，并且在基底中形成源极接触。

公开(公告)号：US5066606A

公开(公告)日：1991-11-19

申请号：US624166

申请日：1990-12-07

申请人： Ruojia Lee

发明人： Ruojia Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10873

摘要： An implant method to develop a storage node access MOSFET to a 3-dimensional stacked capacitor storage cell during a semiconductor fabrication process. This implant method utilizes one layer of oxide to serve as both a MOSFET's (N-channel or P-channel) lightly doped drain spacer as well as a subsequent polysilicon etch stopper when etching a FET's digitline. As DRAM density increases the use of only one oxide layer decreases oxide bridging or buildup.

摘要翻译： 一种在半导体制造过程中将存储节点存取MOSFET开发到三维堆叠电容器存储单元的注入方法。 这种注入方法利用一层氧化物作为MOSFET的（N沟道或P沟道）轻掺杂漏极间隔物以及随后的多晶硅蚀刻阻挡层，当蚀刻FET的数字线时。 随着DRAM密度增加，仅使用一个氧化物层减少氧化物桥接或积聚。

公开(公告)号：US5037773A

公开(公告)日：1991-08-06

申请号：US612296

申请日：1990-11-08

申请人： Ruojia Lee ,  Fernando Gonzalez

发明人： Ruojia Lee ,  Fernando Gonzalez

IPC分类号： H01L21/02 ,  H01L21/3215

CPC分类号： H01L28/84 ,  H01L21/32155 ,  Y10S148/133

摘要： A technique for effectively doping a storage node capacitor plate constructed from low temperature deposited rugged polysilicon. A phosphorus silica glass is deposited prior polysilicon deposition and used primarily to uniformly diffuse n-type dopants into the subsequently deposited rugged poly capacitor plate. This doping technique eliminates the need for high temperature doping and will maintain the rugged surface in the poly of the capacitor plate.

摘要翻译： 一种有效掺杂由低温沉积的多晶硅构成的存储节点电容器板的技术。 在多晶硅沉积之前沉积磷石英玻璃，并主要用于将n型掺杂剂均匀地扩散到随后沉积的耐久性多晶硅电容器板中。 该掺杂技术消除了对高温掺杂的需要，并且将保持电容器板的多晶硅中的粗糙表面。

公开(公告)号：US07057285B2

公开(公告)日：2006-06-06

申请号：US10931181

申请日：2004-08-30

申请人： Ruojia Lee ,  Ralph Kauffman ,  J. Dennis Keller

发明人： Ruojia Lee ,  Ralph Kauffman ,  J. Dennis Keller

IPC分类号： H01L21/20

CPC分类号： H01L27/10888 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/10811 ,  H01L28/91

摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

摘要翻译： 一个铝互连件，其与堆叠的电容器结构相邻延伸并且与堆叠的电容器结构绝缘，以促进半导体器件结构的半导体衬底的有源器件区域与在半导体衬底之上延伸的位线之间的电连通。 铝互连件设置在沟槽内，并且可以包括邻近有源器件区域的金属硅化物层以形成掩埋的金属扩散层。 铝互连还可以包括设置在金属硅化物和铝之间的金属氮化物层。 本发明还包括制造邻近叠层电容器结构的铝互连和包括铝互连的半导体器件结构的方法。

公开(公告)号：US5257238A

公开(公告)日：1993-10-26

申请号：US728486

申请日：1991-07-11

申请人： Ruojia Lee ,  Fernando Gonzalez

发明人： Ruojia Lee ,  Fernando Gonzalez

IPC分类号： G11C11/408 ,  G11C8/00 ,  H03K17/687

CPC分类号： G11C11/4085

摘要： A dynamic memory having improved cell access transistor turn-off state. In order to reduce subthreshold leakage current through cell access devices, the wordline signal voltage is alternates between V.sub.CC (the access transistor turn-on voltage) and a negative potential, rather than between V.sub.CC and ground potential. By applying a negative potential to the wordline during the period when the cell access transistor is required to be in an "off" state, V.sub.GS is made more negative, which results in more complete turn off of the access transistor during the period when the cell capacitor is storing charge. The negative potential replaces ground potential as the pull-down voltage input for signal-inverting wordline drivers. The negative potential may be derived from an existing charge pump used to negatively backbias the substrate, or it may be derived from a dedicated charge pump. However, in order to eliminate the potential problem of current injection, the two negative voltages should be approximately equal. In order to implement the preferred embodiment of this invention, a masked adjustment implant is performed so that the V.sub.T of N-channel cell access transistors within the memory array remains unchanged, while the V.sub.T of the wordline driver N-channel pull-down transistors is raised by an amount substantially equal to V.sub.BB, the backbias voltage.

摘要翻译： 具有改善的单元存取晶体管截止状态的动态存储器。 为了减少通过电池接入装置的次阈值泄漏电流，字线信号电压在VCC（存取晶体管导通电压）和负电位之间交替，而不是在VCC和地电位之间。 在单元存取晶体管需要处于“关”状态的期间，通过对字线施加负电位，使VGS变为负，从​​而导致存储晶体管在单元 电容器正在储存电荷。 负电位将替代地电位作为信号反转字线驱动器的下拉电压输入。 负电位可以从用于负反向衬底的现有电荷泵导出，或者可以从专用电荷泵导出。 然而，为了消除电流注入的潜在问题，两个负电压应近似相等。 为了实现本发明的优选实施例，执行掩蔽调整注入，使得存储器阵列内的N沟道单元存取晶体管的VT保持不变，而字线驱动器N沟道下拉晶体管的VT为 提高了一个基本上等于VBB的量，反向电压。

公开(公告)号：US5241206A

公开(公告)日：1993-08-31

申请号：US955941

申请日：1992-10-02

申请人： Ruojia Lee ,  Monte Manning

发明人： Ruojia Lee ,  Monte Manning

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.

摘要翻译： 开发了用于半导体器件的自对准垂直固有电阻。 自对准垂直固有电阻可用于各种设计中，例如用作集成电路中的上拉器件，更具体地用作SRAM器件中的上拉电阻。 固有电阻的垂直定位不仅占用更小的管芯空间，而且还允许通过消除在植入常规制造工艺中使用的固有电阻之前通常需要的光掩模步骤来构建电阻的简单工艺。