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    Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline
    1.
    发明授权
    Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline 有权
    使用垂直集成的凹槽接入设备和数字线形成DRAM阵列的方法

    公开(公告)号：US08716116B2

    公开(公告)日：2014-05-06

    申请号：US12721373

    申请日：2010-03-10

    申请人： Kunal Parekh ,  Ceredig Roberts ,  Thy Tran ,  Jim Jozwiak ,  David Hwang

    发明人： Kunal Parekh ,  Ceredig Roberts ,  Thy Tran ,  Jim Jozwiak ,  David Hwang

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10891 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10885

    摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

    摘要翻译： 公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。 掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。 埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

    Memory cell layout and process flow
    2.
    发明申请
    Memory cell layout and process flow 有权
    存储单元格布局和流程

    公开(公告)号：US20070045712A1

    公开(公告)日：2007-03-01

    申请号：US11219349

    申请日：2005-09-01

    申请人： Gordon Haller ,  David Hwang ,  Sanh Tang ,  Ceredig Roberts

    发明人： Gordon Haller ,  David Hwang ,  Sanh Tang ,  Ceredig Roberts

    IPC分类号： H01L29/788

    CPC分类号： H01L21/3088 ,  H01L21/0338 ,  H01L27/0207 ,  H01L27/10891 ,  H01L27/10894

    摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5 F, while the digit line pitch is about 3 F.

    摘要翻译： 存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。 至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。 数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。 存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。 字线间距约为1.5 F，而数字线间距约为3 F。

    Methods of forming capacitors, and methods of forming DRAM circuitry
    3.
    发明授权
    Methods of forming capacitors, and methods of forming DRAM circuitry 失效
    形成电容器的方法以及形成DRAM电路的方法

    公开(公告)号：US07071058B2

    公开(公告)日：2006-07-04

    申请号：US10817548

    申请日：2004-04-02

    申请人： Martin Ceredig Roberts ,  Christophe Pierrat

    发明人： Martin Ceredig Roberts ,  Christophe Pierrat

    IPC分类号： H01L21/8242 ,  H01L21/20

    CPC分类号： H01L27/10855 ,  H01L28/91

    摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.

    摘要翻译： 描述了电容器，DRAM电路及其形成方法。 在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。 第二容器与节点位置连接并且具有限定第二内部区域的开口。 这些区域以不重叠的关系彼此间隔开。 电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。 在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。 轴是不同的并且彼此间隔开。 在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。 材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。 第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。 在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

    Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry
    4.
    发明授权
    Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry 有权
    电接触导电插塞的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法

    公开(公告)号：US06727139B2

    公开(公告)日：2004-04-27

    申请号：US10273881

    申请日：2002-10-17

    申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

    发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

    IPC分类号： H01L218242

    CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

    摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。

    Dual-masked isolation
    6.
    发明授权
    Dual-masked isolation 失效
    双屏蔽隔离

    公开(公告)号：US5909630A

    公开(公告)日：1999-06-01

    申请号：US86377

    申请日：1998-05-28

    申请人： Ceredig Roberts ,  Werner Juengling

    发明人： Ceredig Roberts ,  Werner Juengling

    IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/32 ,  H01L21/76221

    摘要： A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.

    摘要翻译： 场隔离过程利用两个或更多个隔离形成步骤在半导体衬底上形成有源区。 每个场隔离步骤以减少场氧化物侵蚀的方式形成场隔离的一部分，特别是通过形成场氧化物岛。 现场隔离配置的叠加定义了所需的有效区域。 目前优选的双掩模方法可以使用单个掩蔽叠层进行，或者更优选地使用用于每个隔离掩模的掩蔽堆叠。 本隔离过程进一步允许针对同一集成电路上的各种隔离要求进行优化的隔离特性。

    Integrated circuits and SRAM memory cells
    7.
    发明授权
    Integrated circuits and SRAM memory cells 失效
    集成电路和SRAM存储单元

    公开(公告)号：US5907176A

    公开(公告)日：1999-05-25

    申请号：US960874

    申请日：1997-10-30

    申请人： Martin Ceredig Roberts

    发明人： Martin Ceredig Roberts

    IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/11

    CPC分类号： H01L28/20 ,  H01L27/0802 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S438/979

    摘要： The invention encompasses integrated circuits and SRAM cells. In one aspect, the invention includes an integrated circuit comprising: a) an electrically insulative pillar extending substantially vertically outward of an underlying layer, the pillar having opposing substantially vertical side surfaces and a top, the pillar being taller than it is wide; b) a resistor comprising a layer of material which extends along both pillar vertical surfaces and over the top of the pillar; c) a first node in electrical connection with the resistor on one side of the insulative pillar; and d) a second node in electrical connection with the resistor on the other side of the insulative pillar.

    摘要翻译： 本发明包括集成电路和SRAM单元。 一方面，本发明包括一种集成电路，包括：a）电绝缘柱，其基本上垂直向下延伸到底层的外侧，所述柱具有相对的基本上垂直的侧表面和顶部，所述柱比其宽; b）电阻器，其包括沿着所述支柱垂直表面延伸并且在所述柱的顶部上方延伸的材料层; c）与绝缘柱的一侧上的电阻器电连接的第一节点; 以及d）与绝缘柱的另一侧上的电阻器电连接的第二节点。

    Method of making a resistor
    9.
    发明授权
    Method of making a resistor 失效
    制作电阻的方法

    公开(公告)号：US5770496A

    公开(公告)日：1998-06-23

    申请号：US788617

    申请日：1997-01-24

    申请人： Martin Ceredig Roberts

    发明人： Martin Ceredig Roberts

    IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/11 ,  H01L27/02

    CPC分类号： H01L28/20 ,  H01L27/0802 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S438/979

    摘要： A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.

    摘要翻译： 从半导体材料形成电阻器的半导体处理方法包括：a）提供与电阻器进行电连接的节点; b）在节点外部提供第一电绝缘材料; c）在所述节点外部的所述第一电绝缘材料中提供暴露的垂直侧壁; d）在所述第一材料的外部和所述第一材料垂直侧壁上方提供第二电绝缘材料，所述第一和第二材料可相对于彼此选择性地蚀刻; e）相对于所述第一材料选择性地各向异性地蚀刻所述第二材料，以在所述第一材料垂直侧壁上方形成基本上垂直延伸的侧壁隔离物，并且向外暴露所述邻近所述侧壁间隔物的所述第一材料，所述间隔件具有内表面和外表面; f）相对于第二材料选择性地蚀刻第一材料以向外暴露间隔件外表面的至少一部分; g）在所述暴露的外隔离物表面上并在所述内间隔件表面上提供半导体材料的保形层，所述共形层与所述节点形成电连接; 以及h）将所述保形层图案化成所需的电阻器形状。 公开了SRAM和其它集成电路的集成电路。