-
41.发明授权System on a chip bus with automatic pipeline stage insertion for timing closure 有权系统具有自动流水线插入的片上总线，用于定时关闭公开(公告)号：US06834378B2
公开(公告)日：2004-12-21
申请号：US10264162
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F945
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译： 一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。 芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。 相对于默认传播时间确定信号从源设备传播到目的地设备的时间。 然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。 每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。 使用附加逻辑，当管道级插入各种路径时，不需要更改设备。 寄存器被用作插入到路径内的流水线级。
-
42.发明授权公开(公告)号：US06826656B2
公开(公告)日：2004-11-30
申请号：US10059537
申请日：2002-01-28
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1208
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0831 , Y02D10/14
摘要： A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.
摘要翻译： 一种用于在基于窥探缓存的环境中降低功耗的方法和系统。 存储器可以经由总线耦合到多个处理单元。 每个处理单元可以包括耦合到与处理单元相关联的高速缓存器的高速缓存控制器。 高速缓存控制器可以包括包括N个比特的分段寄存器，其中分段寄存器中的每个比特可以与划分成N个分段的一段存储器相关联。 高速缓存控制器可以被配置为窥探总线上的所请求的地址。 一旦确定段寄存器中的哪个位与被窥探的请求地址相关联，则段寄存器可以确定是否设置与被窥探的请求地址相关联的位。 如果该位未设置，则可能不执行高速缓存搜索，从而减轻与窥探请求高速缓存搜索相关联的功耗。
-
43.发明授权公开(公告)号：US07330941B2
公开(公告)日：2008-02-12
申请号：US11088383
申请日：2005-03-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F2212/1028 , Y02D10/13
摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.
摘要翻译： 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中是否有任何复制条目包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含修改后的数据，则从内存中读取的数据将被写入所选条目，而无需先读入条目。 在一个银行缓存中，两个或多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否能够提高处理器性能并降低功耗。
-
公开(公告)号：US06907502B2
公开(公告)日：2005-06-14
申请号：US10264169
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
CPC分类号： G06F12/0831
摘要： A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.
摘要翻译： 一种用于将窥探优先级的方法推送到在请求FIFO内调度请求的数据处理系统中。 接收到的每个新请求被置于请求FIFO的最后位置，并且请求FIFO通常仅基于请求FIFO内的顺序授予请求。 由于先前请求被顺序授权，所以随后的请求更接近请求FIFO的第一位置。 然而，当在请求FIFO处接收到窥探推送时，窥探推送将自动插入请求FIFO的第一个位置，而在请求FIFO之前尚未被授予请求。
-
45.发明授权公开(公告)号：US06807608B2
公开(公告)日：2004-10-19
申请号：US10077560
申请日：2002-02-15
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.
摘要翻译： 用于执行可变大小的存储器一致性事务的方法和系统。 耦合在从机和主机之间的总线接口单元可以被配置为从主机接收包括多个相干性颗粒的请求（主请求）。 系统中的每个窥探单元可以被配置为一次窥探主请求中的不同数量的一致性粒子。 一旦总线接口单元已经从每个窥探逻辑单元接收到指示集合的指示集合，指示主请求中的相关性集合的集合已被每个监听单元窥探，并且用于收集相关性颗粒的地址上的数据 被侦听未被更新，总线接口单元可以允许未更新的那些一致性粒度的地址上的数据在请求主机和从机之间传送。
-
46.发明授权Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target 失效当第一个请求从目标接收到重试响应时，将FIFO请求队列内的第一请求重新排序到不同的队列位置公开(公告)号：US07035958B2
公开(公告)日：2006-04-25
申请号：US10264170
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F13/36
CPC分类号： G06F13/362 , G06F13/4022 , G06F2213/0038
摘要： A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO. In the latter implementation, the controller logic of the bus controller messages the initiator when a request has been retried and subsequently removed from the first position of the request FIFO. The initiator then determines whether or not to re-issue the request.
摘要翻译： 一种操作芯片上系统（SoC）的请求FIFO的方法，其中已经被许可的第一个位置的请求和随后从预期目标接收到重试的请求自动地按照下面的其他请求重新排序 它在请求FIFO中。 每个发出的请求被标记为启用或禁用重新排序功能。 当被标记为启用重新排序的请求被授予时，FIFO逻辑监视为请求提供的响应。 如果响应是重试，则请求从请求FIFO的第一位置移除，并且下一个顺序请求被移动到第一位置。 删除的请求可以在请求FIFO内重新排序或发送回发起者。 在前面的实现中，控制器逻辑重新排序请求FIFO中的第一个请求。 在后一实现中，总线控制器的控制器逻辑在请求已被重试并随后从请求FIFO的第一位置移除时消息发起者。 然后，启动器确定是否重新发出请求。
-
公开(公告)号：US20080189506A1
公开(公告)日：2008-08-07
申请号：US11672066
申请日：2007-02-07
申请人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F12/1027 , G06F2212/655 , Y02D10/13
摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
摘要翻译： 通过识别导致存储器中的不同页面之间的边界交叉的地址以及链接与两个存储器页面相关联的地址转换信息来改进处理器内的地址转换性能。 根据处理器的一个实施例，处理器包括被配置为识别对跨越第一和第二存储器页之间的页边界的存储区的访问的电路。 电路还被配置为链接与第一和第二存储器页相关联的地址转换信息。 因此，响应于后续访问相同的存储器区域，可以基于单个地址转换来检索与第一和第二存储器页面相关联的地址转换信息。
-
48.发明授权System on a chip bus with automatic pipeline stage insertion for timing closure 失效系统具有自动流水线插入的片上总线，用于定时关闭公开(公告)号：US07296175B2
公开(公告)日：2007-11-13
申请号：US10971947
申请日：2004-10-22
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译： 一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。 芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。 相对于默认传播时间确定信号从源设备传播到目的地设备的时间。 然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。 每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。 使用附加逻辑，当管道级插入各种路径时，不需要更改设备。 寄存器被用作插入到路径内的流水线级。
-
49.发明申请Methods and Systems for Checking Run-Time Integrity of Secure Code Cross-Reference to Related Applications 有权用于检查安全代码交叉引用到相关应用程序的运行时完整性的方法和系统公开(公告)号：US20090313695A1
公开(公告)日：2009-12-17
申请号：US12485089
申请日：2009-06-16
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。
-
50.发明授权Methods and systems for checking run-time integrity of secure code cross-reference to related applications 有权用于检查安全代码的运行时完整性的方法和系统交叉引用到相关应用程序公开(公告)号：US08639943B2
公开(公告)日：2014-01-28
申请号：US12485089
申请日：2009-06-16
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。
-
-
-
-
-
-
-
-
-
搜索结果
114 条记录 (耗时 0.028 秒)
