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    Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory
    42.
    发明授权
    Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory 失效
    制造用作非易失性随机存取存储器中的存储器单元的器件结构的方法

    公开(公告)号：US07700428B2

    公开(公告)日：2010-04-20

    申请号：US12117950

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7881 ,  H01L27/1203 ,  H01L29/66825

    摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

    摘要翻译： 制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。 该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，并且部分地移除第二半导体本体以限定邻近 第一半导体体的通道。 该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极， 与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

    Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit
    44.
    发明授权
    Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit 失效
    使用绝缘体上半导体衬底制造的有源器件的器件结构和用于射频集成电路的设计结构

    公开(公告)号：US07709926B2

    公开(公告)日：2010-05-04

    申请号：US12108924

    申请日：2008-04-24

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7436 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

    摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

    摘要翻译： 用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。 器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域 比第一深度，以及半导体层中的第一掺杂区域。 第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。 装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。

    Integrated antifuse structure for FINFET and CMOS devices
    45.
    发明授权
    Integrated antifuse structure for FINFET and CMOS devices 有权
    用于FINFET和CMOS器件的集成反熔丝结构

    公开(公告)号：US07087499B2

    公开(公告)日：2006-08-08

    申请号：US10539333

    申请日：2002-12-20

    申请人： Jed H. Rankin ,  Wagdi W. Abadeer ,  Jeffrey S. Brown ,  William R. Tonti

    发明人： Jed H. Rankin ,  Wagdi W. Abadeer ,  Jeffrey S. Brown ,  William R. Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/785

    摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111–114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t–114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

    摘要翻译： 描述了与半导体器件（例如FINFET或平面CMOS器件）集成的制造和反熔丝结构（100）的方法。 设置在设置在基板（10）上的绝缘体（3）上的半导体材料（11）的区域; 蚀刻工艺暴露了半导体材料中的多个拐角（111-114）。 露出的角部被氧化，以形成角落处的细长尖端（111t-114t）; 去除顶部上方的氧化物（31）。 然后在半导体材料上形成氧化物层（例如栅极氧化物），并覆盖在角部上; 该层在拐角处具有减小的厚度。 在角部处形成与氧化物层（51）接触的导电材料层（60），从而通过氧化物层在半导体材料和导电材料层之间形成多个可能的击穿路径。 将诸如老化电压的电压施加到结构将至少一个击穿路径转换成导电路径（103,280）。

    Integrated circuit amplifier device and method using FET tunneling gate current
    46.
    发明授权
    Integrated circuit amplifier device and method using FET tunneling gate current 失效
    集成电路放大器器件及使用FET隧道栅极电流的方法

    公开(公告)号：US07167053B2

    公开(公告)日：2007-01-23

    申请号：US10904238

    申请日：2004-10-29

    申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Kiran V. Chatty ,  John A. Fifield

    发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Kiran V. Chatty ,  John A. Fifield

    IPC分类号： H03F3/16 ,  H03F3/45 ,  H03G3/12

    CPC分类号： H03F3/16 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45468

    摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.

    摘要翻译： 在示例性实施例中，集成电路放大器包括被配置为具有源极退化的公共源极放大器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器 。 隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极退化的公共源极放大器，以便设置放大器的输出电导。

    Voltage divider for integrated circuits
    47.
    发明授权
    Voltage divider for integrated circuits 失效
    用于集成电路的分压器

    公开(公告)号：US07061308B2

    公开(公告)日：2006-06-13

    申请号：US10605466

    申请日：2003-10-01

    申请人： Wagdi W. Abadeer ,  John A. Fifield ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  John A. Fifield ,  William R. Tonti

    IPC分类号： G05F3/02

    CPC分类号： G11C5/147 ,  H01L27/0802 ,  H01L27/088 ,  H02M3/00

    摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).

    摘要翻译： 用于集成电路的分压器，不包括使用电阻器。 在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET 1和NFET 2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A 1（未示出）的栅电极（16）和p-衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A 2（未示出）的栅电极（24）和p基板（26）。 NFET 1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET 1和NFET 2之间的电压差与VDD具有线性关系。 结果，通过适当地选择各个晶体管栅电极区域（A 1）和（A 2）之间的比率，可以在NFET 1和NFET 2之间划分电压VDD。

    Memory elements and methods of using the same
    48.
    发明授权
    Memory elements and methods of using the same 有权
    内存元素和使用方法

    公开(公告)号：US07916531B2

    公开(公告)日：2011-03-29

    申请号：US12351872

    申请日：2009-01-12

    申请人： Wagdi W. Abadeer ,  Anthony R Bonaccio ,  Jack A Mandelman ,  William R. Tonti ,  Sebastian T Ventrone

    发明人： Wagdi W. Abadeer ,  Anthony R Bonaccio ,  Jack A Mandelman ,  William R. Tonti ,  Sebastian T Ventrone

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0466

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。

    Programmable capacitors and methods of using the same
    49.
    发明授权
    Programmable capacitors and methods of using the same 有权
    可编程电容器及其使用方法

    公开(公告)号：US07358823B2

    公开(公告)日：2008-04-15

    申请号：US11353516

    申请日：2006-02-14

    申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

    发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

    摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。