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公开(公告)号：US07916531B2
公开(公告)日：2011-03-29
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R Bonaccio , Jack A Mandelman , William R. Tonti , Sebastian T Ventrone
发明人： Wagdi W. Abadeer , Anthony R Bonaccio , Jack A Mandelman , William R. Tonti , Sebastian T Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。
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公开(公告)号：US07358823B2
公开(公告)日：2008-04-15
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。
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公开(公告)号：US07477541B2
公开(公告)日：2009-01-13
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。
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公开(公告)号：US20090147568A1
公开(公告)日：2009-06-11
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。
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公开(公告)号：US20080144252A1
公开(公告)日：2008-06-19
申请号：US12037725
申请日：2008-02-26
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H01G7/00
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。
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6.发明授权Digital reliability monitor having autonomic repair and notification capability 有权数字可靠性监控器具有自主修复和通知功能公开(公告)号：US07287177B2
公开(公告)日：2007-10-23
申请号：US10729751
申请日：2003-12-04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译： 一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。
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7.发明授权Digital reliability monitor having autonomic repair and notification capability 有权数字可靠性监控器具有自主修复和通知功能公开(公告)号：US07966537B2
公开(公告)日：2011-06-21
申请号：US12479914
申请日：2009-06-08
IPC分类号： G01R31/28
CPC分类号： G06F1/04
摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.
摘要翻译： 一种用于防止集成电路故障的电路。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。
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8.发明授权Digital reliability monitor having autonomic repair and notification capability 有权数字可靠性监控器具有自主修复和通知功能公开(公告)号：US07823002B2
公开(公告)日：2010-10-26
申请号：US11772418
申请日：2007-07-02
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译： 一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。
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9.发明申请DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY 有权具有自动维修和通知能力的数字可靠性监控器公开(公告)号：US20090254781A1
公开(公告)日：2009-10-08
申请号：US12479914
申请日：2009-06-08
IPC分类号： G06F11/07
CPC分类号： G06F1/04
摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.
摘要翻译： 一种用于防止集成电路故障的电路。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。
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公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。
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