公开(公告)号：US08866509B1

公开(公告)日：2014-10-21

申请号：US13842664

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Robert I. Fu ,  Chi M. Nguyen ,  James M. Simkins ,  Brian C. Gaide ,  Brian D. Philoksky

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Abstract translation: 公开了具有忽略控制信号的选项的具有触发器组的集成电路。 例如，集成电路包括共享公共复位信号的第一组和第二组触发器，以及用于从公共复位信号中选择第一输出的第一选择单元和要发送到的逻辑低电平信号 第二组翻牌。 逻辑低信号的选择用于防止公共复位信号施加到第二组中的触发器。 集成电路还可以包括用于从公共复位信号中选择第二输出的第二选择单元和要发送到第一组触发器的逻辑低信号。 逻辑低信号的选择用于防止公共复位信号施加到第一组中的触发器。

公开(公告)号：US08773164B1

公开(公告)日：2014-07-08

申请号：US13666271

申请日：2012-11-01

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young

IPC: H03K19/173

CPC classification number: H03K19/1776 ,  H03K19/17736

Abstract: In an apparatus, an interconnect block includes a plurality of configuration memory cells. A plurality of multiplexers is respectively coupled to the configuration memory cells. An acknowledge circuit is coupled to the configuration memory cells. The acknowledge circuit includes a plurality of acknowledge inputs. The configuration memory cells are coupled to selectively set states of the plurality of multiplexers and correspondingly selectively activate inputs of the plurality of acknowledge inputs. A data ready circuit is coupled to at least one multiplexer output of the plurality of multiplexers.

Abstract translation: 在一种装置中，互连块包括多个配置存储单元。 多个复用器分别耦合到配置存储器单元。 确认电路耦合到配置存储器单元。 确认电路包括多个确认输入。 配置存储器单元被耦合以选择性地设置多个多路复用器的状态，并且相应地选择性地激活多个确认输入的输入。 数据就绪电路耦合到多个复用器的至少一个复用器输出端。