公开(公告)号：US08866509B1

公开(公告)日：2014-10-21

申请号：US13842664

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Robert I. Fu ,  Chi M. Nguyen ,  James M. Simkins ,  Brian C. Gaide ,  Brian D. Philoksky

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Abstract translation: 公开了具有忽略控制信号的选项的具有触发器组的集成电路。 例如，集成电路包括共享公共复位信号的第一组和第二组触发器，以及用于从公共复位信号中选择第一输出的第一选择单元和要发送到的逻辑低电平信号 第二组翻牌。 逻辑低信号的选择用于防止公共复位信号施加到第二组中的触发器。 集成电路还可以包括用于从公共复位信号中选择第二输出的第二选择单元和要发送到第一组触发器的逻辑低信号。 逻辑低信号的选择用于防止公共复位信号施加到第一组中的触发器。

公开(公告)号：US09871520B1

公开(公告)日：2018-01-16

申请号：US15237439

申请日：2016-08-15

Applicant: Xilinx, Inc.

Inventor： Chi M. Nguyen ,  Robert I. Fu

IPC: H03K19/003 ,  H03K19/177 ,  H03K3/356

CPC classification number: H03K19/00392 ,  H03K3/356104 ,  H03K19/17764 ,  H03K19/23

Abstract: The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.

公开(公告)号：US10284185B1

公开(公告)日：2019-05-07

申请号：US15845957

申请日：2017-12-18

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Ilya K. Ganusov ,  Chi M. Nguyen ,  Robert I. Fu

IPC: H03K5/15 ,  G06F1/10 ,  G06F1/12 ,  H03K19/096 ,  H03K5/00

Abstract: The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.