公开(公告)号：US4302783A

公开(公告)日：1981-11-24

申请号：US100344

申请日：1979-12-05

申请人： Soichiro Mima ,  Hiroshi Matsushima ,  Yasuharu Shimeki ,  Nobuyoshi Kihara

发明人： Soichiro Mima ,  Hiroshi Matsushima ,  Yasuharu Shimeki ,  Nobuyoshi Kihara

IPC分类号： G11B20/12 ,  G11B5/09 ,  G11B20/18 ,  G11B20/20 ,  G11B5/02

CPC分类号： G11B5/09 ,  G11B20/1803 ,  G11B20/20

摘要： At least one bit of a digital signal including a plurality of bits to be simultaneously recorded on a plurality of tracks of a magnetic tape, is recorded on at least two tracks located at opposite sides with respect to a reference track. The reference track carries a reference signal utilized for producing a synchronous signal with which the plurality of bits are reproduced in synchronization. When reproducing, a.c. signals derived from the two corresponding tracks having the simultaneously recorded bits are added to each other whereby the phase difference of the plurality of bits with respect to the reference signal is compensated while drop out phenomenon is reduced.

摘要翻译： 包括要同时记录在磁带的多个轨道上的多个位的数字信号的至少一位被记录在相对于参考轨道位于相对侧的至少两个磁道上。 参考轨道携带用于产生同步信号的参考信号，同步信号同步地再现多个位。 再现时， 从具有同时记录的比特的两个对应轨道导出的信号彼此相加，从而相对于参考信号的多个比特的相位差被补偿，同时丢弃现象减少。

公开(公告)号：US4027274A

公开(公告)日：1977-05-31

申请号：US589546

申请日：1975-06-23

申请人： Kiyotake Fukui ,  Hiroshi Matsushima ,  Yukinobu Ishigaki

发明人： Kiyotake Fukui ,  Hiroshi Matsushima ,  Yukinobu Ishigaki

IPC分类号： H03L7/10 ,  H03L7/14 ,  H03C3/06

CPC分类号： H03L7/10 ,  H03L7/148 ,  Y10S331/02

摘要： A phase locked loop circuit comprises a phase comparator having an operation range with specific limits for phase comparing. A voltage-controlled oscillator produces an output at the output of the phase locked loop. At the same time, the oscillator output is fed to the phase comparator. A detector circuit, supplied with the output of the phase comparator, detects any exceeding of a specific limit of the phase by comparing the operation range of the phase comparator with a phase deviation of the oscillator output signal fed to the phase comparator. The detector produces an output correction voltage. An adder circuit adds this output correction voltage and an output error voltage of the phase comparator and supplies the resulting added voltage, as a control voltage, to the voltage-controlled oscillator. This phase locked loop operates in a state wherein the lock range thereof has been equivalently expanded by the correction voltage.

摘要翻译： 锁相环电路包括具有用于相位比较的特定限制的操作范围的相位比较器。 压控振荡器在锁相环的输出端产生一个输出。 同时，振荡器输出被馈送到相位比较器。 提供有相位比较器的输出的检测器电路通过将相位比较器的操作范围与馈送到相位比较器的振荡器输出信号的相位偏差进行比较来检测超过相位的特定极限。 检测器产生输出校正电压。 加法器电路将该输出校正电压和相位比较器的输出误差电压相加，并将所得到的附加电压作为控制电压提供给压控振荡器。 该锁相环在其锁定范围已被等效地扩大了校正电压的状态下工作。