公开(公告)号：US08044653B2

公开(公告)日：2011-10-25

申请号：US11757865

申请日：2007-06-04

Applicant: Philippe Maige ,  Yannick Guedon

Inventor： Philippe Maige ,  Yannick Guedon

IPC: G05F3/16

CPC classification number: G05F1/575

Abstract: A low drop-out DC voltage regulator regulates a voltage from a DC supply and includes: a pass device controllable to maintain a voltage at an output of the regulator and arranged to provide a first current from the DC supply, at least part of said first current being provided to a load coupled to the output of the regulator; and a current regulator coupled to said pass device and to the output of the regulator. The current regulator is arranged to conduct a second current controllable such that the first current through said pass device remains constant irrespective of variations in a load current to said load.

Abstract translation: 低压差直流电压调节器调节来自直流电源的电压，并且包括：通过装置，其可控制以在调节器的输出端保持电压并被布置成提供来自DC电源的第一电流，所述第一 电流被提供到耦合到调节器的输出的负载; 以及耦合到所述通过装置和调节器的输出的电流调节器。 电流调节器被布置成传导可控的第二电流，使得通过所述通过装置的第一电流保持恒定，而与负载电流的变化无关。

公开(公告)号：US20110234310A1

公开(公告)日：2011-09-29

申请号：US13070285

申请日：2011-03-23

Applicant: Jean-Pierre Blanc

Inventor： Jean-Pierre Blanc

IPC: H03K5/1252

CPC classification number: H03H11/12 ,  H03H11/04

Abstract: A low-pass filter, including: between a first terminal and a second terminal, a series association of a first resistor, of a second resistor, and of a first amplifier; in parallel with the second resistor, a series association of a second amplifier and of a first capacitor; a second capacitor between an input of the first amplifier and a third terminal of application of a reference voltage; and a third capacitor between the second terminal and the third terminal.

Abstract translation: 一种低通滤波器，包括：在第一端子和第二端子之间，第一电阻器，第二电阻器和第一放大器的串联; 与第二电阻器并联的第二放大器和第一电容器的串联; 在第一放大器的输入端和施加参考电压的第三端子之间的第二电容器; 以及在第二端子和第三端子之间的第三电容器。

公开(公告)号：US20110221944A1

公开(公告)日：2011-09-15

申请号：US13045211

申请日：2011-03-10

Applicant: Benoît Deschamps

Inventor： Benoît Deschamps

IPC: H04N5/335

CPC classification number: H04N5/35536 ,  H04N5/35545 ,  H04N5/35554 ,  H04N5/363 ,  H04N5/374

Abstract: The disclosure relates to a process of controlling a pixel cell of an image sensor of the CMOS type, comprising the steps of: initializing a sense node and a read node of the pixel cell; partially transferring electrical charges accumulated at the sense node to the read node; completely evacuating electrical charges accumulated at the read node; partially transferring electrical charges accumulated at the sense node to the read node; measuring the electrical charges accumulated at the read node to obtain a pixel signal corresponding to a quantity of electrical charges accumulated during a short integration period; completely transferring electrical charges accumulated at the sense node to the read node, without a prior initialization of the read node, and measuring the electrical charges at the read node to obtain a pixel voltage corresponding thus to the sum of the electrical charges accumulated during the short and long integration periods.

Abstract translation: 本发明涉及一种控制CMOS型图像传感器的像素单元的过程，包括以下步骤：初始化像素单元的感测节点和读取节点; 将在感测节点处累积的电荷部分地转移到读节点; 完全排除在读取节点处累积的电荷; 将在感测节点处累积的电荷部分地转移到读节点; 测量在所述读取节点处累积的电荷，以获得与在短积分期间期间累积的电荷量对应的像素信号; 将在感测节点处累积的电荷完全转移到读取节点，而不读取节点的先前初始化，并且测量读取节点处的电荷，以获得对应于在短暂期间累积的电荷的总和的像素电压 和长整合期。

公开(公告)号：US20110214012A1

公开(公告)日：2011-09-01

申请号：US13090140

申请日：2011-04-19

Applicant: Frédéric Bancel ,  Nicolas Berard

Inventor： Frédéric Bancel ,  Nicolas Berard

IPC: G06F11/20

CPC classification number: G06F11/28

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract translation: 协处理器包括用于执行至少一个命令的计算单元和一个固化设备。 安全设备包括用于监视命令的执行以检测任何执行错误的错误检测电路，一旦执行命令开始，将协处理器默认放入错误模式，并且在结束时提升错误模式 执行命令，如果没有检测到错误，则用于监视要检测的至少一个事件的外观的事件检测电路，以及用于在不发生检测事件的情况下屏蔽错误模式的屏蔽电路;以及 如果在协处理器处于错误模式时发生事件，则将错误模式声明为协处理器的外部。 尤其应用于嵌入在智能卡集成电路中的协处理器。

公开(公告)号：US20110213944A1

公开(公告)日：2011-09-01

申请号：US13022099

申请日：2011-02-07

Applicant: Giuseppe Guarnaccia ,  Raffaele Guarrasi ,  Radhia Kacem

Inventor： Giuseppe Guarnaccia ,  Raffaele Guarrasi ,  Radhia Kacem

IPC: G06F12/00

CPC classification number: G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Abstract translation: 同步系统包括存储器和控制电路。 所述控制电路包括用于以第一时钟信号在所述存储器中写入数据的写入接口，其中所述写入接口被配置为响应写入命令与写入指针一起操作;读取接口，用于以第二时钟信号从所述存储器读取数据 时钟信号，其中所述读取接口被配置为响应于读取命令而与读取指针一起操作，用于使所述写入指针和所述读取指针与同步等待时间同步的同步电路，以及用于在存储器中用 精细延迟，其中精细延迟小于同步等待时间。

公开(公告)号：US20110194734A1

公开(公告)日：2011-08-11

申请号：US13044385

申请日：2011-03-09

Applicant: Fabrice Gensolen ,  Lionel Martin ,  Guy Cathebras

Inventor： Fabrice Gensolen ,  Lionel Martin ,  Guy Cathebras

IPC: G06K9/00

CPC classification number: G06T7/20 ,  H04N5/23248 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23264

Abstract: A method for capturing a sequence of video images, using an imager including an estimation of the parameters of a model of global motion between successive images. The method may include measurement of local motions on edges of the images, with the estimation of the parameters of the global motion model performed using the result of the measurement of local motions on the edges of the images.

Abstract translation: 一种使用包括对连续图像之间的全局运动模型的参数的估计的成像器捕获视频图像序列的方法。 该方法可以包括使用图像边缘上的局部运动的测量结果来对全局运动模型的参数的估计来估计图像边缘上的局部运动。

公开(公告)号：US07971040B2

公开(公告)日：2011-06-28

申请号：US11567998

申请日：2006-12-07

Applicant: Renaud Ayrignac ,  Isabelle Sename

Inventor： Renaud Ayrignac ,  Isabelle Sename

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/4812 ,  G06F9/30043 ,  G06F9/3861

Abstract: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.

Abstract translation: 本公开涉及一种用于由处理器执行用于保存/恢复处理器的多个内部寄存器的指令的方法。 该方法包括分解保存/恢复指令以产生用于保存/恢复寄存器的内容的微指令，执行每个微指令，初始化寄存器的保存/恢复进度状态，更新进度状态 在每次生成用于保存/恢复寄存器的微指令时的保存/恢复，在保存/恢复寄存器的中断的情况下保存进度状态以执行更高优先级的任务，并恢复进度 恢复寄存器的保存/恢复时的状态。

公开(公告)号：US07958175B2

公开(公告)日：2011-06-07

申请号：US11653185

申请日：2007-01-12

Applicant: Alain Pomet ,  Benjamin Duval ,  Robert Leydier

Inventor： Alain Pomet ,  Benjamin Duval ,  Robert Leydier

IPC: G06F1/02

CPC classification number: G06F7/588

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract translation: 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。

公开(公告)号：US07916449B2

公开(公告)日：2011-03-29

申请号：US12134490

申请日：2008-06-06

Applicant: Sébastien Cremer ,  Philippe Delpech ,  Sylvie Bruyere

Inventor： Sébastien Cremer ,  Philippe Delpech ,  Sylvie Bruyere

IPC: H01G4/06

CPC classification number: H01L28/87 ,  H01L28/91 ,  Y10T29/417

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract translation: 用于形成具有至少一个二维或三维电容器的微电子器件的方法包括在衬底上产生多个部件和多个叠加的金属互连电平。 在金属互连层上形成绝缘层，在其中形成有一个或多个由该绝缘层形成的绝缘块的下一个金属互连层的水平金属区。 该区域被设计成形成电容器的下部结构部分。

公开(公告)号：US07892927B2

公开(公告)日：2011-02-22

申请号：US11725160

申请日：2007-03-16

Applicant: Stephane Monfray ,  Thomas Skotnicki ,  Didier Dutartre ,  Alexandre Talbot

Inventor： Stephane Monfray ,  Thomas Skotnicki ,  Didier Dutartre ,  Alexandre Talbot

IPC: H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/66628 ,  H01L29/66772

Abstract: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.

Abstract translation: 包括富含锗的通道的晶体管。 通过从所述中间层的下表面开始的硅 - 锗中间层中包含的硅的氧化产生富锗的通道。 因此锗原子迁移到硅 - 锗中间层的上表面，并被栅极绝缘层阻挡。 因此，在氧化步骤期间原子的迁移对晶体管的性能的影响较小，因为晶体管的栅极绝缘体已经被制造并且在该步骤期间不被修改。 锗原子向固定的栅极绝缘体的迁移导致通道和绝缘体之间的表面缺陷的限制。