公开(公告)号：US20140240962A1

公开(公告)日：2014-08-28

申请号：US13775352

申请日：2013-02-25

申请人： Connie WANG ,  Wei Hung YU

发明人： Connie WANG ,  Wei Hung YU

IPC分类号： F21V33/00

CPC分类号： A47G23/02 ,  A47G19/2227 ,  A47G2019/2238

摘要： This invention provides a cup with twinkling light effects, primarily comprising an inner cup, an outer cup, and a light unit, with the lower half of the inner cup having a number of arched convex strips, and the base of which has diamond-facet of concave and convex cones. As a result, when the light unit at the base of the outer cup is activated, the effects of the arched convex strips and diamond facets cause the cup to produce numerous refractions of the light source, creating twinkling rays of light with dazzling variation.

摘要翻译： 本发明提供一种具有闪烁光效果的杯，主要包括内杯，外杯和灯单元，内杯的下半部具有多个拱形凸条，并且其底部具有金刚石面 的凹凸锥。 结果，当外杯底部的灯单元被激活时，拱形凸条和金刚石面的影响使杯子产生许多光源的折射，从而产生闪烁的光线，具有耀眼的变化。

公开(公告)号：USD698955S1

公开(公告)日：2014-02-04

申请号：US29439600

申请日：2012-12-13

申请人： Connie Wang ,  Wei Hung Yu

设计人： Connie Wang ,  Wei Hung Yu

公开(公告)号：USD667515S1

公开(公告)日：2012-09-18

申请号：US29359490

申请日：2010-04-12

申请人： Connie Wang

设计人： Connie Wang

公开(公告)号：US20090023263A1

公开(公告)日：2009-01-22

申请号：US11779465

申请日：2007-07-18

申请人： Tony Phan ,  Kyle M. Flessner ,  Martin B. Mollat ,  Connie Wang ,  Arthur Pan ,  Eric William Beach ,  Michelle R. Keramidas ,  Karen Elizabeth Burks

发明人： Tony Phan ,  Kyle M. Flessner ,  Martin B. Mollat ,  Connie Wang ,  Arthur Pan ,  Eric William Beach ,  Michelle R. Keramidas ,  Karen Elizabeth Burks

IPC分类号： H01L21/02

CPC分类号： H01L28/20 ,  H01L21/8221 ,  H01L27/0688

摘要： A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.

摘要翻译： 一种用于制造半导体器件的方法，该方法包括通过包括在半导体衬底上沉积电阻材料层的工艺来形成薄膜电阻器。 该方法还包括在电阻材料层上沉积绝缘层，以及在绝缘层上进行第一干蚀刻工艺以形成绝缘体。 该方法还包括在电阻材料层上执行第二干蚀刻工艺以形成电阻体。 电阻体和绝缘体具有基本相同的周长。

公开(公告)号：US06979903B1

公开(公告)日：2005-12-27

申请号：US10608883

申请日：2003-06-26

申请人： Steven C. Avanzino ,  Pin-Chin Connie Wang ,  Minh Van Ngo

发明人： Steven C. Avanzino ,  Pin-Chin Connie Wang ,  Minh Van Ngo

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76826 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76841 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit. This allows a selective conversion of dielectric materials with no diffusion barrier properties to be converted into good barrier materials which allows larger channels and shrinkage of the integrated circuit.

摘要翻译： 提供具有半导体器件的半导体衬底的集成电路。 形成在半导体衬底上的电介质层具有设置在其中的开口。 电介质层是能够改变为阻挡介电材料的非阻挡介电材料。 开口周围的电介质层变成阻挡电介质材料，并且沉积导体芯材以填充开口。 处理导体芯以形成用于集成电路的通道。 这允许不具有扩散阻挡性质的电介质材料的选择性转化被转换成允许集成电路的较大通道和收缩的良好阻隔材料。

公开(公告)号：US06893955B1

公开(公告)日：2005-05-17

申请号：US10328347

申请日：2002-12-24

申请人： Sergey D. Lopatin ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Pin-Chin Connie Wang

IPC分类号： H01L23/532 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路制造方法。 在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。 阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。 无核屏障层对开口进行排列，并且导体芯填充无核阻挡层上的开口。 阻挡层沉积在开口中并且包含键合到电介质层的阻挡材料的原子层，结合到阻挡材料层和导体芯的中间材料以及与中间材料结合的导体芯材料。 导体芯与导体芯材料结合。

公开(公告)号：US06710452B1

公开(公告)日：2004-03-23

申请号：US09618964

申请日：2000-07-19

申请人： Pin-Chin Connie Wang ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Amit P. Marathe

发明人： Pin-Chin Connie Wang ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Amit P. Marathe

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.

摘要翻译： 提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。 阻挡层具有比通道介电层更加负的形成热量，由此阻挡层与导体芯的材料扩散到沟道介电层上形成阻挡层。 阻挡层还与导体芯形成稳定的化合物，以形成将沟道电介质结合到导体芯的相干势垒层。

公开(公告)号：US06621290B1

公开(公告)日：2003-09-16

申请号：US09905283

申请日：2001-07-13

申请人： Amit P. Marathe ,  Pin-Chin Connie Wang

发明人： Amit P. Marathe ,  Pin-Chin Connie Wang

IPC分类号： G01R3126

CPC分类号： H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor layer. A dielectric layer is placed over the semiconductor material. Conductive top and bottom layers are placed over the dielectric layer and the bottom of the semiconductor wafer. The conductive top layer is connected to the electrical ground. The conductive bottom layer is connected to the source of electrical potential. The current flow is measured from the conductive bottom layer to the conductive top layer.

摘要翻译： 用于测试半导体材料的测试结构和方法设置有具有电接地和电势源的半导体晶片。 导体层放置在半导体晶片上方，半导体材料放置在导体层上。 介电层放置在半导体材料上。 导电顶层和底层放置在电介质层和半导体晶片的底部之上。 导电顶层连接到电气接地。 导电底层连接到电位源。 从导电底层到导电顶层测量电流。

公开(公告)号：US06566248B1

公开(公告)日：2003-05-20

申请号：US09759114

申请日：2001-01-11

申请人： Pin-Chin Connie Wang ,  Minh Quoc Tran

发明人： Pin-Chin Connie Wang ,  Minh Quoc Tran

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/76877

摘要： A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core with a random grain texture fills the opening over the barrier layer. The crystallographic orientation of the conductor core is then graphoepitaxially changed to reduce its random grain texture.

摘要翻译： 为具有半导体器件的半导体衬底的集成电路提供制造方法。 在半导体衬底上形成器件电介质层。 器件电介质层上的沟道电介质层具有形成在其中的开口。 屏障层对通道开口进行排列。 具有随机晶粒纹理的导体芯填充阻挡层上的开口。 然后将导体芯的晶体取向作为薄膜表面改变以减少其随机晶粒纹理。

公开(公告)号：US06472757B2

公开(公告)日：2002-10-29

申请号：US09758994

申请日：2001-01-11

申请人： Amit P. Marathe ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo

发明人： Amit P. Marathe ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo

IPC分类号： H01L23528

CPC分类号： H01L21/76844 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.