公开(公告)号：US12068197B2

公开(公告)日：2024-08-20

申请号：US17234136

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC分类号： H01L21/768 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC分类号： H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

摘要： A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US12018378B2

公开(公告)日：2024-06-25

申请号：US16485543

申请日：2018-06-21

申请人： KOJIMA CHEMICALS, CO., LTD.

发明人： Tomohito Kato ,  Hideto Watanabe

IPC分类号： C23C18/34 ,  C23C18/16 ,  C23C18/44 ,  H01L21/768

CPC分类号： C23C18/44 ,  C23C18/1651 ,  C23C18/34 ,  H01L21/7685 ,  H01L21/76874

摘要： An object is to provide an electroless plating process which can thin a film thickness of a nickel film and can obtain a film having excellent mounting characteristics, when the nickel film and a gold film are sequentially formed on a surface of a copper material. In order to solve the above-mentioned problems, provided is an electroless plating process which sequentially forms a nickel film and a gold film on a surface of a copper material by an electroless plating method and includes: a step of forming the nickel film on the surface of the copper material by an electroless strike plating method; and a step of forming the gold film by a reduction-type electroless plating method.

公开(公告)号：US20240063138A1

公开(公告)日：2024-02-22

申请号：US18226786

申请日：2023-07-27

申请人： WALTON ADVANCED ENGINEERING, INC.

发明人： HONG-CHI YU ,  CHUN-JUNG LIN ,  RUEI-TING GU

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L23/552 ,  H01L24/32 ,  H01L23/3128 ,  H01L23/3675 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76874 ,  H01L2224/32225 ,  H01L2924/1811 ,  H01L2924/3025

摘要： A chip package having four sides provided with electromagnetic interference (EMI) shielding layers correspondingly and a method of manufacturing the same are provided. The four EMI shielding layers are made of metals, located on four lateral sides of the chip package, and completely covering four lateral sides of a substrate and four lateral sides of an insulating layer to prevent at least one first circuit layer, at least one second circuit layer, and at least one chip from electromagnetic interference. Moreover, the EMI shielding layers help to improve heat dissipation efficiency of the first circuit layer, the second circuit layer, and the chip.

公开(公告)号：US10083949B2

公开(公告)日：2018-09-25

申请号：US15223862

申请日：2016-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Yi-Jou Lin

IPC分类号： H01L25/00 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L21/288 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/288 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/18 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.

公开(公告)号：US20180151503A1

公开(公告)日：2018-05-31

申请号：US15877751

申请日：2018-01-23

申请人： Lam Research Corporation

发明人： Artur Kolics ,  William T. Lee ,  Larry Zhao ,  Derek Wong ,  Praveen Nalla ,  Kaihan Ashtiani ,  Patrick A. Van Cleemput ,  Yezdi Dordi

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/285 ,  H01L23/522 ,  H01L21/02

CPC分类号： H01L23/53238 ,  C23C16/26 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

公开(公告)号：US09875968B2

公开(公告)日：2018-01-23

申请号：US15442307

申请日：2017-02-24

申请人： Lam Research Corporation

发明人： Artur Kolics ,  William T. Lee ,  Larry Zhao ,  Derek Wong ,  Praveen Nalla ,  Kaihan Ashtiani ,  Patrick A. Van Cleemput ,  Yezdi Dordi

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/02 ,  H01L21/288 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/53238 ,  C23C16/26 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

公开(公告)号：US20170167029A1

公开(公告)日：2017-06-15

申请号：US15372787

申请日：2016-12-08

申请人： Tokyo Electron Limited

发明人： Tomohisa Hoshino ,  Keiichi Fujita ,  Masato Hamada

IPC分类号： C23C18/40 ,  C23C18/18 ,  C23C18/16 ,  C23C18/34

CPC分类号： C23C18/40 ,  C23C18/1619 ,  C23C18/1632 ,  C23C18/1675 ,  C23C18/1879 ,  C23C18/1882 ,  C23C18/34 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H05K3/422

摘要： A substrate processing apparatus can allow palladium atoms to be coupled to a surface of a substrate without performing a silane coupling processing with a silane coupling agent on the substrate. In a substrate processing apparatus 1, a plating unit 4 includes a catalyst solution supply unit 43a and a plating liquid supply unit 45. The catalyst solution supply unit 43a forms a catalyst layer 91 on a surface of a substrate W1 by supplying, onto the substrate W1, a catalyst solution L1 containing a complex of a palladium ion and a monocyclic 5- or 6-membered aromatic or aliphatic heterocyclic compound having one or two nitrogen atoms as a heteroatom. After the catalyst solution L1 is supplied, the plating liquid supply unit 45 forms an electroless plating layer 92 on the catalyst layer 91 formed on a substrate W2 by supplying a plating liquid M1 onto the substrate W2.

公开(公告)号：US20170162512A1

公开(公告)日：2017-06-08

申请号：US15442307

申请日：2017-02-24

申请人： Lam Research Corporation

发明人： Artur Kolics ,  William T. Lee ,  Larry Zhao ,  Derek Wong ,  Praveen Nalla ,  Kaihan Ashtiani ,  Patrick A. Van Cleemput ,  Yezdi Dordi

IPC分类号： H01L23/532 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L21/288

CPC分类号： H01L23/53238 ,  C23C16/26 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

公开(公告)号：US09653350B2

公开(公告)日：2017-05-16

申请号：US14548794

申请日：2014-11-20

申请人： Tokyo Electron Limited

发明人： Takashi Tanaka ,  Nobutaka Mizutani ,  Yusuke Saito ,  Mitsuaki Iwashita

IPC分类号： B05D3/00 ,  H01L21/768 ,  C23C18/18 ,  B05D3/02 ,  B05D3/10 ,  C23C18/40 ,  C23C18/48

CPC分类号： H01L21/76874 ,  B05D3/002 ,  B05D3/02 ,  B05D3/10 ,  C23C18/1893 ,  C23C18/40 ,  C23C18/48 ,  H01L21/76898

摘要： Catalytic metal nanoparticles can be attached on a base. A pre-treatment method for plating includes a catalytic particle-containing film forming process of forming a catalytic particle-containing film on a surface of a substrate by supplying, onto the substrate, a catalytic particle solution which is prepared by dispersing the catalytic metal nanoparticles and a dispersing agent in a solvent containing water; a first heating process of removing moisture contained at least in the catalytic particle-containing film by heating the substrate to a first temperature; and a second heating process of polymerizing the dispersing agent to have a sheet shape by heating the substrate to a second temperature higher than the first temperature after the first heating process and fixing the catalytic metal nanoparticles on a base layer by covering the catalytic metal nanoparticles with the sheet-shaped dispersing agent.

公开(公告)号：US09589896B2

公开(公告)日：2017-03-07

申请号：US15067033

申请日：2016-03-10

申请人： IMEC VZW

发明人： Silvia Armini

IPC分类号： H01L21/00 ,  H01L23/532 ,  C23C18/12 ,  C23C18/20 ,  H01L21/768

CPC分类号： H01L23/53238 ,  C23C18/12 ,  C23C18/20 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76862 ,  H01L21/76874

摘要： An electronic circuit structure comprising a substrate, a dielectric layer on top of the substrate and comprising a cavity having side-walls, a manganese or manganese nitride layer covering the side-walls, and a self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.

摘要翻译： 一种电子电路结构，包括基底，位于基底顶部的电介质层，包括具有侧壁的空腔，覆盖侧壁的锰或氮化锰层，以及自组装单层，其包含式 ZLA，覆盖锰或氮化锰层，其中Z选自伯胺基，羧酸基，硫醇基，硒酚基和在该循环中具有未取代的叔胺的杂环基，其中 L是包含1至12个碳原子和0至3个杂原子的有机连接体，其中A是将连接体连接到锰或氮化锰层的基团。