公开(公告)号：US20240332168A1

公开(公告)日：2024-10-03

申请号：US18736859

申请日：2024-06-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JUNG-HSING CHIEN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/40 ,  H10B12/00

CPC classification number: H01L23/5226 ,  H01L21/76852 ,  H01L29/401 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H10B12/0335 ,  H10B12/485

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. An upper portion of the first conductive plug extends into the second dielectric layer. The semiconductor device structure further includes a silicide layer disposed in the second dielectric layer and covering a top surface and sidewalls of the upper portion of the first conductive plug, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug and the silicide layer.

公开(公告)号：US12080593B2

公开(公告)日：2024-09-03

申请号：US17859981

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/3212

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US11978704B2

公开(公告)日：2024-05-07

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

公开(公告)号：US11955424B2

公开(公告)日：2024-04-09

申请号：US18093540

申请日：2023-01-05

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Benjamin David Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76883 ,  H01L23/53252 ,  H01L2221/1047

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

公开(公告)号：US11929366B2

公开(公告)日：2024-03-12

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0673

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20240014133A1

公开(公告)日：2024-01-11

申请号：US18343127

申请日：2023-06-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/528 ,  H01L21/764 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/764 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/32133 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/31111 ,  H01L23/522 ,  H01L23/53295 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76897 ,  H01L21/76804 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53271 ,  H01L23/5329 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/76885 ,  H01L21/76834

Abstract: An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

公开(公告)号：US11854979B2

公开(公告)日：2023-12-26

申请号：US17379000

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun Lee ,  Min Joo Lee ,  Wan Don Kim ,  Hyeon Jin Shin ,  Hyun Bae Lee ,  Hyun Seok Lim

IPC: H01L23/532 ,  H10B12/00 ,  H01L21/768

CPC classification number: H01L23/53252 ,  H01L23/53276 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H01L21/76885

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

公开(公告)号：US20230361042A1

公开(公告)日：2023-11-09

申请号：US18357500

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

公开(公告)号：US20230343707A1

公开(公告)日：2023-10-26

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US11742239B2

公开(公告)日：2023-08-29

申请号：US17501523

申请日：2021-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.