公开(公告)号：US07355651B2

公开(公告)日：2008-04-08

申请号：US10945828

申请日：2004-09-21

申请人： Richard H. Wyman ,  Darren Neuman

发明人： Richard H. Wyman ,  Darren Neuman

IPC分类号： H04N7/01

CPC分类号： H04N7/012 ,  H04N5/144

摘要： In a video system, a method and system for minimizing both on-chip memory size and peak DRAM bandwidth requirements for multi-field deinterlacers are provided. Present line pixels and absent line pixels may be determined and may be ordered into upper line pixels and lower line pixels based on whether an interlaced output frame is top field or bottom field originated. Upper line pixels may be buffered in an upper line FIFO that may hold half a video line and lower line pixels may be buffered in an lower line FIFO that may hold a video line. A source switch and a line length counter may be used to assemble the deinterlaced output frame by selecting from the buffered upper line pixels and the buffered lower line pixels. The deinterlaced output frame may be buffered in an output FIFO.

摘要翻译： 在视频系统中，提供了用于最小化多场去隔行器的片上存储器大小和DRAM带宽峰值峰值的方法和系统。 可以基于隔行输出帧是顶场还是底场来确定当前行像素和不存在线像素，并且可以将其排序为上行像素和下行像素。 上行像素可以被缓冲在可以保持一半视频行的上行FIFO中，并且较低行像素可以被缓冲在可能保持视频行的下行FIFO中。 源开关和行长度计数器可用于通过从缓冲的上行像素和缓冲的下行像素中选择来组合去隔行输出帧。 去隔行输出帧可以在输出FIFO中缓冲。

公开(公告)号：US20080062200A1

公开(公告)日：2008-03-13

申请号：US11936426

申请日：2007-11-07

申请人： David Baer ,  Darren Neuman

发明人： David Baer ,  Darren Neuman

IPC分类号： G09G5/00

CPC分类号： G09G5/377 ,  G09G5/005 ,  G09G5/06 ,  G09G5/08 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/0407 ,  G09G2340/0421 ,  G09G2340/0442 ,  G09G2360/02

摘要： Systems and methods that provide graphics using a graphical engine are provided. In one example, a system may provide layered graphics in a video environment. The system may include a bus, a graphical engine and a graphical pipeline. The graphical engine may be coupled to the bus and may be adapted to composite a plurality of graphical layers into a composite graphical layer. The graphical engine may include a memory that stores the composite graphical layer. The graphical pipeline may be coupled to the bus and may be adapted to transport the composite graphical layer.

摘要翻译： 提供了使用图形引擎提供图形的系统和方法。 在一个示例中，系统可以在视频环境中提供分层图形。 该系统可以包括总线，图形引擎和图形管线。 图形引擎可以耦合到总线，并且可以适于将多个图形层合成为复合图形层。 图形引擎可以包括存储复合图形层的存储器。 图形流水线可以耦合到总线，并且可以适于传输复合图形层。

公开(公告)号：US07274403B2

公开(公告)日：2007-09-25

申请号：US10875422

申请日：2004-06-24

申请人： Darren Neuman ,  Richard H. Wyman

发明人： Darren Neuman ,  Richard H. Wyman

IPC分类号： H04N7/01 ,  H04N9/74

CPC分类号： H04N7/012 ,  H04N7/0137

摘要： A system and method that scales interlaced video fields with different sizes in a deinterlacer. The deinterlacer may expect video fields of a certain size. The input to the system may be a video stream of interlaced content, with fields having different sizes depending on the video content. The method scales the input video fields to the appropriate size expected by the deinterlacer. The expected size of the fields may be programmable. The method may provide an output with the expected size of black pixels in the absence of an input to the system.

摘要翻译： 一种在去交错器中对具有不同大小的隔行扫描视频场进行缩放的系统和方法。 去隔行器可能期望视频字段具有一定的大小。 系统的输入可以是隔行内容的视频流，根据视频内容，字段具有不同的大小。 该方法将输入视频字段缩放到去隔行扫描器预期的适当大小。 字段的预期大小可以是可编程的。 该方法可以在没有对系统的输入的情况下提供具有黑色像素的预期大小的输出。

公开(公告)号：US20070139425A1

公开(公告)日：2007-06-21

申请号：US11304281

申请日：2005-12-15

申请人： Darren Neuman

发明人： Darren Neuman

IPC分类号： G06F13/14

CPC分类号： G09G5/02 ,  G09G2340/0407 ,  G09G2340/0442 ,  G09G2340/125 ,  G09G2360/02 ,  H04N5/45 ,  H04N7/0122 ,  H04N7/0125 ,  H04N21/4122 ,  H04N21/4316 ,  H04N21/4402 ,  H04N21/4621

摘要： Certain aspects of a system and method for handling video data may comprise determining data rates associated with each of a plurality of destination devices utilized for processing video data in a video processing system that supports multiple display data rates. A data rate associated with a first portion of the plurality of destination devices may be adjusted to match at least one data rate associated with one or more of a remaining portion of the plurality of destination devices in instances where the determined data rate of the first portion of the plurality of destination devices is greater than one or more data rate associated with one or more of the remaining portion of the plurality of destination devices.

摘要翻译： 用于处理视频数据的系统和方法的某些方面可以包括确定与支持多个显示数据速率的视频处理系统中用于处理视频数据的多个目的地设备中的每一个相关联的数据速率。 在第一部分的确定的数据速率的情况下，可以调整与多个目的地设备的第一部分相关联的数据速率以匹配与多个目的地设备的剩余部分中的一个或多个相关联的至少一个数据速率 多个目的地设备中的一个或多个与多个目的地设备的剩余部分中的一个或多个相关联的大于一个或多个数据速率。

公开(公告)号：US07149954B2

公开(公告)日：2006-12-12

申请号：US10646717

申请日：2003-08-25

申请人： Darren Neuman ,  Chengfuh Jeffrey Tang ,  Yao-Hua Steven Tseng ,  Guang Ting Shih ,  Wen Huang ,  Charles Thomas Monahan

发明人： Darren Neuman ,  Chengfuh Jeffrey Tang ,  Yao-Hua Steven Tseng ,  Guang Ting Shih ,  Wen Huang ,  Charles Thomas Monahan

IPC分类号： H03M13/09 ,  H04N7/64

CPC分类号： G06F11/1004 ,  H04L1/246

摘要： Provided is a system and method for performing CRC analysis in a video test bench. An exemplary system includes a memory configured for storing a required number representative of the data fields to be analyzed. A module is coupled at least indirectly to the memory and configured for (i) receiving an input data stream, (ii) performing cyclic redundancy check (CRC) analysis of the received data stream, and (iii) producing an output representative of an actual number of received data fields analyzed. The input data stream includes synchronization markers defining boundaries of each of the received data fields. Next, a comparator is configured for (i) comparing the required number and the actual number and (ii) producing a disabling signal when the actual number matches the required number. A detector is coupled to the comparator and configured for (i) receiving the input data stream and sensing a presence of the synchronization markers, (ii) receiving the disabling signal, and (iii) disabling the CRC module when the disabling signal is received.

摘要翻译： 提供了一种用于在视频测试台中执行CRC分析的系统和方法。 示例性系统包括被配置为存储要分析的数据字段的所需数量的存储器。 模块至少间接耦合到存储器并且被配置用于（i）接收输入数据流，（ii）对所接收的数据流执行循环冗余校验（CRC）分析，以及（iii）产生代表实际的 分析的接收数据字段数。 输入数据流包括定义每个接收的数据字段的边界的同步标记。 接下来，比较器被配置为（i）比较所需数量和实际数量，以及（ii）当实际数量与所需数量匹配时产生禁用信号。 检测器耦合到比较器并且被配置用于（i）接收输入数据流并感测同步标记的存在，（ii）接收禁用信号，以及（iii）当接收到禁用信号时禁用CRC模块。

公开(公告)号：US20060269166A1

公开(公告)日：2006-11-30

申请号：US11333557

申请日：2006-01-17

申请人： Sheng Zhong ,  Darren Neuman ,  Brian Schoner

发明人： Sheng Zhong ,  Darren Neuman ,  Brian Schoner

IPC分类号： G06K9/32 ,  G06K9/40

CPC分类号： G06T3/4007

摘要： Certain embodiments of the invention may be found in a system and method for implementing graphics and a video scaling algorithm using interpolation based on symmetrical polyphase filtering. A video or graphics scaler may be utilized to scale luma, chroma, and/or alpha information in a video image. The scaler may comprise a first symmetric polyphase sub-filter with zero phase shift that generates an in-phase filtered pixel and a second symmetric polyphase sub-filter that generates an out-of-phase filtered pixel. The video scaler may also comprise an interpolator that may generate a scaled video image pixel based on the generated in-phase and out-of-phase filtered pixels and a scaling factor. The scaling factor may be determined based on an input video size (M) and a desired output video size (N). The interpolation of the generated in-phase and out-of-phase pixels in the video scaler may be implemented by utilizing a Farrow structure.

摘要翻译： 本发明的某些实施例可以在使用基于对称多相滤波的插值来实现图形和视频缩放算法的系统和方法中找到。 可以使用视频或图形缩放器来缩放视频图像中的亮度，色度和/或阿尔法信息。 缩放器可以包括具有零相移的第一对称多相子滤波器，其产生同相滤波的像素，以及产生异相滤波像素的第二对称多相子滤波器。 视频缩放器还可以包括内插器，其可以基于产生的同相和异相滤波像素和缩放因子来生成缩放视频图像像素。 缩放因子可以基于输入视频大小（M）和期望的输出视频大小（N）来确定。 可以通过利用Farrow结构来实现视频缩放器中产生的同相和异相像素的插值。

公开(公告)号：US20050168635A1

公开(公告)日：2005-08-04

申请号：US10945828

申请日：2004-09-21

申请人： Richard Wyman ,  Darren Neuman

发明人： Richard Wyman ,  Darren Neuman

IPC分类号： H04N5/14 ,  H04N9/74

CPC分类号： H04N7/012 ,  H04N5/144

摘要： In a video system, a method and system for minimizing both on-chip memory size and peak DRAM bandwidth requirements for multi-field deinterlacers are provided. Present line pixels and absent line pixels may be determined and may be ordered into upper line pixels and lower line pixels based on whether an interlaced output frame is top field or bottom field originated. Upper line pixels may be buffered in an upper line FIFO that may hold half a video line and lower line pixels may be buffered in an lower line FIFO that may hold a video line. A source switch and a line length counter may be used to assemble the deinterlaced output frame by selecting from the buffered upper line pixels and the buffered lower line pixels. The deinterlaced output frame may be buffered in an output FIFO.

摘要翻译： 在视频系统中，提供了用于最小化多场去隔行器的片上存储器大小和DRAM带宽峰值峰值的方法和系统。 可以基于隔行输出帧是顶场还是底场来确定当前行像素和不存在线像素，并且可以将其排序为上行像素和下行像素。 上行像素可以被缓冲在可以保持一半视频行的上行FIFO中，并且较低行像素可以被缓冲在可能保持视频行的下行FIFO中。 源开关和行长度计数器可用于通过从缓冲的上行像素和缓冲的下行像素中选择来组合去隔行输出帧。 去隔行输出帧可以在输出FIFO中缓冲。

公开(公告)号：US20050039204A1

公开(公告)日：2005-02-17

申请号：US10641031

申请日：2003-08-15

申请人： Darren Neuman ,  Patrick Law ,  Alek Movshovich ,  Chuck Monahan

发明人： Darren Neuman ,  Patrick Law ,  Alek Movshovich ,  Chuck Monahan

IPC分类号： H04N5/44 ,  H04N5/46 ,  H04N5/913 ,  H04N5/91 ,  H04N7/167

CPC分类号： H04N21/426 ,  H04N5/4401 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N2005/91364

摘要： Systems and methods for filtering to comply with copy-protection regulations set forth for HDTV signals by the MPAA are presented. A copy-protection filter constrains the resolution of the HDTV signal when copy-protection bits are present in a video signal. The copy-protection filter may be placed in an analog data stream before the video signal is converted from a digital to an analog signal. A second copy-protection filter is optionally placed in a digital data stream. The copy-protection filter may be combined with other filters in a video encoder, or with a scaler before the input video data stream enters a compositor.

摘要翻译： 介绍了过滤符合MPAA为HDTV信号制定的复制保护规定的系统和方法。 当复制保护位存在于视频信号中时，复制保护滤波器限制HDTV信号的分辨率。 复制保护滤波器可以在视频信号从数字转换成模拟信号之前被放置在模拟数据流中。 第二个复制保护滤波器可选地放置在数字数据流中。 复制保护滤波器可以与输入视频数据流进入合成器之前的视频编码器中的其它滤波器或缩放器组合。

公开(公告)号：US20050039102A1

公开(公告)日：2005-02-17

申请号：US10646717

申请日：2003-08-25

申请人： Darren Neuman ,  Chengfuh Tang ,  Yao-Hua Tseng ,  Guang Shih ,  Wen Huang

发明人： Darren Neuman ,  Chengfuh Tang ,  Yao-Hua Tseng ,  Guang Shih ,  Wen Huang

IPC分类号： G06F11/10 ,  H04L1/00 ,  H04L1/24 ,  H04N19/89 ,  H03M13/00

CPC分类号： G06F11/1004 ,  H04L1/246

摘要： Provided is a system and method for performing CRC analysis in a video test bench. An exemplary system includes a memory configured for storing a required number representative of the data fields to be analyzed. A module is coupled at least indirectly to the memory and configured for (i) receiving an input data stream, (ii) performing cyclic redundancy check (CRC) analysis of the received data stream, and (iii) producing an output representative of an actual number of received data fields analyzed. The input data stream includes synchronization markers defining boundaries of each of the received data fields. Next, a comparator is configured for (i) comparing the required number and the actual number and (ii) producing a disabling signal when the actual number matches the required number. A detector is coupled to the comparator and configured for (i) receiving the input data stream and sensing a presence of the synchronization markers, (ii) receiving the disabling signal, and (iii) disabling the CRC module when the disabling signal is received.

摘要翻译： 提供了一种用于在视频测试台中执行CRC分析的系统和方法。 示例性系统包括被配置为存储要分析的数据字段的所需数量的存储器。 模块至少间接耦合到存储器并且被配置用于（i）接收输入数据流，（ii）对所接收的数据流执行循环冗余校验（CRC）分析，以及（iii）产生代表实际的 分析的接收数据字段数。 输入数据流包括定义每个接收的数据字段的边界的同步标记。 接下来，比较器被配置为（i）比较所需数量和实际数量，以及（ii）当实际数量与所需数量匹配时产生禁用信号。 检测器耦合到比较器并且被配置用于（i）接收输入数据流并感测同步标记的存在，（ii）接收禁用信号，以及（iii）当接收到禁用信号时禁用CRC模块。

公开(公告)号：US06243664B1

公开(公告)日：2001-06-05

申请号：US09181084

申请日：1998-10-27

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： G06F15173

CPC分类号： H03K19/17736 ,  G06F17/5054 ,  G06F17/5077 ,  Y10T307/74

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列被耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。