公开(公告)号：US06243664B1

公开(公告)日：2001-06-05

申请号：US09181084

申请日：1998-10-27

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： G06F15173

CPC分类号： H03K19/17736 ,  G06F17/5054 ,  G06F17/5077 ,  Y10T307/74

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列被耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。

公开(公告)号：US5689686A

公开(公告)日：1997-11-18

申请号：US822769

申请日：1997-03-21

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： H04Q3/545 ,  H04Q3/68 ,  H04Q11/04 ,  H04Q3/04

CPC分类号： H04Q11/0407 ,  H04Q11/04 ,  H04Q3/545 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1305 ,  H04Q2213/13141 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  Y10T307/74 ,  Y10T307/76

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。

公开(公告)号：US5848066A

公开(公告)日：1998-12-08

申请号：US705990

申请日：1996-08-30

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： H03K19/173 ,  H03K19/177 ,  H04Q11/04

CPC分类号： H03K19/17736 ,  H03K19/1737

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

公开(公告)号：US5923868A

公开(公告)日：1999-07-13

申请号：US957003

申请日：1997-10-23

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Newman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Newman

IPC分类号： H04Q3/545 ,  H04Q3/68 ,  H04Q11/04 ,  G06F15/173 ,  G06F17/16

CPC分类号： H04Q11/0407 ,  H04Q11/04 ,  H04Q3/545 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1305 ,  H04Q2213/13141 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  Y10T307/74 ,  Y10T307/76

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。

公开(公告)号：US20100172175A1

公开(公告)日：2010-07-08

申请号：US12724219

申请日：2010-03-15

申请人： Hagop A. Nazarian

发明人： Hagop A. Nazarian

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641 ,  G11C2211/5643 ,  G11C2211/5647

摘要： A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.

摘要翻译： 非易失性存储器件以使寄生信号的耦合最小化的方式对每行中的存储器单元进行编程。 控制逻辑单元使用通过评估要写入行中的单元的数据而选择的一组位状态分配来对行中的单元进行编程。 控制逻辑单元通过确定将被编程到与写入数据相对应的多个位状态中的每一个的行中的单元数目来执行该评估。 然后，控制逻辑单元选择一组位状态分配，这将使得分配给每个位状态的编程电平成为与位状态编程的行中的存储单元的数量成反比。 所选择的位状态集合然后用于对行中的存储器单元进行编程。

公开(公告)号：US07697324B2

公开(公告)日：2010-04-13

申请号：US12272590

申请日：2008-11-17

申请人： Hagop A. Nazarian

发明人： Hagop A. Nazarian

IPC分类号： G11C16/10

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641 ,  G11C2211/5643 ,  G11C2211/5647

摘要： A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.

摘要翻译： 非易失性存储器件以使寄生信号的耦合最小化的方式对每行中的存储器单元进行编程。 控制逻辑单元使用通过评估要写入行中的单元的数据而选择的一组位状态分配来对行中的单元进行编程。 控制逻辑单元通过确定将被编程到与写入数据相对应的多个位状态中的每一个的行中的单元数目来执行该评估。 然后，控制逻辑单元选择一组位状态分配，这将使得分配给每个位状态的编程电平成为与位状态编程的行中的存储单元的数量成反比。 所选择的位状态集合然后用于对行中的存储器单元进行编程。

公开(公告)号：US07688630B2

公开(公告)日：2010-03-30

申请号：US12370810

申请日：2009-02-13

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US07425742B2

公开(公告)日：2008-09-16

申请号：US11495245

申请日：2006-07-28

申请人： Hagop A. Nazarian

发明人： Hagop A. Nazarian

IPC分类号： H01L29/788

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30

摘要： NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rds resistance and decreased “narrow width” effect, allowing for increased scaling of NAND memory cell strings. In addition, the required voltages for reading and programming operations are reduced, allowing the use of more efficient, lower voltage charge pumps and a reduction circuit element feature sizes and layouts. Cell inhibit of unselected cells is also increased, reducing the likelihood of cell disturb in the memory array. Operation speed is improved by increasing read current of the selected NAND string and by increasing the ability to overcome the RC time constants of circuit lines and capacitances through lowered voltage swings and increased current supplies.

摘要翻译： NAND架构描述了利用连续的信道增强和耗尽型浮动栅极存储器单元的闪存串，存储器阵列和存储器件。 耗尽模式浮栅存储器单元允许通过较低通道r ds电阻增加的单元电流和减小的“窄宽度”效应，从而允许增加NAND存储器单元串的缩放。 此外，读取和编程操作所需的电压降低，允许使用更有效，更低电压的电荷泵和降低电路元件特征尺寸和布局。 未选择的细胞的细胞抑制也增加，降低了存储器阵列中细胞干扰的可能性。 通过增加所选NAND串的读取电流并通过降低的电压摆幅和增加的电流供应来提高克服电路线和电容的RC时间常数的能力来提高操作速度。

公开(公告)号：US07286378B2

公开(公告)日：2007-10-23

申请号：US10873112

申请日：2004-06-23

申请人： Hagop A. Nazarian

发明人： Hagop A. Nazarian

IPC分类号： G11C27/00

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C7/067 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0061 ,  G11C2213/78 ,  G11C2213/79

摘要： A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently.

公开(公告)号：US07064970B2

公开(公告)日：2006-06-20

申请号：US10699652

申请日：2003-11-04

申请人： Hagop A. Nazarian

发明人： Hagop A. Nazarian

IPC分类号： G11C27/00

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C2213/78 ,  G11C2213/79

摘要： A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells connected thereto into one half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where n is an even number of at least 2; there may or may not be an equal number of cells on either side of the transistor. The memory array has memory cells, which are grouped into 1T-2nCell blocks.

摘要翻译： 一种适用于可变电阻存储器的存储器阵列架构，其通过将与所寻址的单元相关联的存储器单元的数量限制为具有潜行路径电阻的已知数量来减轻潜行路径和相关问题，所述已知数量可以在感测所寻址的存储器时被计算和考虑 细胞。 存储器单元的块与存取晶体管相关联，存取晶体管将连接到其的存储单元分成单元块的一半（1/2）段。 存取晶体管可以与n个存储器单元相关联，其中n是至少2的偶数; 在晶体管的任一侧上可能有也可能没有相同数量的单元。 存储器阵列具有存储单元，其被分组为1T-2nCell块。