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公开(公告)号：US20080117221A1
公开(公告)日：2008-05-22
申请号：US10845662
申请日：2004-05-14
IPC分类号： G06T1/20
CPC分类号： G06T15/40 , G06F9/3867 , G06F9/3869 , G06T15/005 , G06T2200/28
摘要： A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows. Any of a number of downstream pipestages may remove the occluded pixel information, and in response thereto, may notify a gatekeeper pipestage of the slack increase so that more pixels can be allowed into the pipeline.
摘要翻译： 一种像素处理系统和方法，其允许使用包括减少的门数和低功率操作的浅图形管线来呈现复杂的三维图像。 像素分组信息包括在单个统一数据获取阶段检索的像素表面属性值。 如果像素分组信息有助于图像显示呈现（例如，可以执行Z值的深度比较），则确定。 根据确定的结果处理像素分组信息处理。 如果像素表面属性值被遮挡，则像素表面属性值和像素分组信息从进一步处理中去除。 在一个示例性实现中，像素分组包括多个行，并且对于多个行来协调处理。 多个下游管道中的任何一个可以去除遮挡的像素信息，并且响应于此，可以通知网守管道的松弛增加，使得可以允许更多的像素进入流水线。
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公开(公告)号：US07280112B1
公开(公告)日：2007-10-09
申请号：US10846788
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3867 , G09G3/003 , G09G5/363 , G09G2340/145 , G09G2360/125
摘要： An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.
摘要翻译： 描述图形处理器中的算术逻辑单元（ALU）。 ALU包括用于使用第一组像素数据执行操作的电路。 第一组像素数据驻留在耦合到电路的流水线寄存器中。 临时寄存器耦合到电路。 临时寄存器可以接收到操作结果。 临时寄存器允许使用一组像素数据生成的结果与同一ALU中的后续像素数据集一起使用。 因此，可以在第二组像素数据的第二操作中使用操作的结果，该第二组像素数据位于第一组像素数据之后的流水线寄存器中。
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公开(公告)号：US07091982B2
公开(公告)日：2006-08-15
申请号：US10846097
申请日：2004-05-14
申请人： Edward A. Hutchins , Brian K. Angell , Paul Kim
发明人： Edward A. Hutchins , Brian K. Angell , Paul Kim
CPC分类号： G06T15/005 , G06F9/3001 , G06F9/30025 , G06T1/20
摘要： A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.
摘要翻译： 公开了具有用于处理像素分组的可编程算术逻辑单元（ALU）级的图形处理器。 在ALU中执行标量算术运算以实现图形功能。
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54.发明授权Circuit and method for displaying images using multisamples of non-uniform color resolution 有权使用非均匀颜色分辨率的多个样本显示图像的电路和方法公开(公告)号：US06614448B1
公开(公告)日：2003-09-02
申请号：US09222441
申请日：1998-12-28
IPC分类号： G06G536
CPC分类号： G06T11/001
摘要： A graphics processor displays pixels in an image at non-uniform resolution, using a maximum resolution in the interior of a surface in the image, and a lower resolution at edges. Higher color resolution in the interior eliminates color aliasing that would otherwise be caused if the interior were displayed at the lower resolution. Lower resolution at the edges is not noticeable to the human eye, and allows the graphics processor to use one or more low resolution color signals in generating the displayed image, thereby reducing hardware (e.g. memory locations required to store such signals, and lines required to route such signals). One such processor (not necessarily a graphics processor) includes a resolution reducer and a resolution enhancer that respectively reduce and enhance the resolution of a signal. Specifically, the resolution reducer reduces the resolution of a high resolution signal to generate a low resolution signal. The resolution enhancer enhances the low resolution signal to generate a signal (called “enhanced resolution signal”) having the same number of bits as the high resolution signal. One such resolution reducer simply drops a number of least significant bits to generate a low resolution signal, and the corresponding resolution enhancer passes, as the enhanced resolution signal, the low resolution signal and the above-described number of least significant bits of a high resolution signal. The enhanced resolution signal is not a significant aspect of one embodiment because in some embodiments the low resolution signal and the high resolution signal are used directly.
摘要翻译： 图形处理器以非均匀分辨率显示图像中的像素，使用图像中表面内部的最大分辨率，以及边缘处较低的分辨率。 内部更高的色彩分辨率消除了如果内部以较低的分辨率显示，否则会引起色彩混叠。 在边缘处较低的分辨率对于人眼不是显着的，并且允许图形处理器在生成显示的图像时使用一个或多个低分辨率彩色信号，从而减少硬件（例如存储这种信号所需的存储器位置，以及所需的线路 路由这样的信号）。 一个这样的处理器（不一定是图形处理器）包括分辨率减小器和分辨率增强器，其分别降低和增强信号的分辨率。 具体地，分辨率降低器降低了高分辨率信号的分辨率以产生低分辨率信号。 分辨率增强器增强了低分辨率信号以产生具有与高分辨率信号相同数量的位的信号（称为“增强分辨率信号”）。 一个这样的分辨率减小器简单地丢弃多个最低有效位以产生低分辨率信号，并且相应的分辨率增强器作为增强分辨率信号通过低分辨率信号和上述数量的高分辨率的最低有效位 信号。 增强分辨率信号不是一个实施例的重要方面，因为在一些实施例中，低分辨率信号和高分辨率信号被直接使用。
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公开(公告)号：US08860722B2
公开(公告)日：2014-10-14
申请号：US12002732
申请日：2007-12-17
CPC分类号： G06T15/005 , G06T1/20 , G06T15/405
摘要： Early Z scoreboard tracking systems and methods in accordance with the present invention are described. Multiple pixels are received and a pixel depth raster operation is performed on the pixels. The pixel depth raster operation comprises discarding a pixel that is occluded. In one exemplary implementation, the depth raster operation is done at a faster rate than a color raster operation. Pixels that pass the depth raster operation are checked for screen coincidence. Pixels with screen coincidence are stalled and pixels without screen coincidence are forwarded to lower stages of the pipeline. The lower stages of the pipeline are programmable and pixel flight time can vary (e.g., can include multiple passes through the lower stages). Execution through the lower stages is directed by a program sequencer which also directs notification to the pixel flight tracking when a pixel is done processing.
摘要翻译： 描述根据本发明的早期Z记分板跟踪系统和方法。 接收多个像素，并对像素执行像素深度光栅操作。 像素深度光栅操作包括丢弃被遮挡的像素。 在一个示例性实现中，深度光栅操作以比彩色光栅操作更快的速度完成。 检查通过深度光栅操作的像素的屏幕重合。 具有屏幕巧合的像素停止，而没有屏幕一致的像素被转发到流水线的较低阶段。 管道的较低级是可编程的，并且像素飞行时间可以变化（例如，可以包括通过下级的多次）。 较低阶段的执行由程序定序器执行，程序定序器还在像素完成处理时指示像素飞行跟踪。
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56.发明授权Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline 有权用于为图形管线实现多个高精度和低精度内插器的方法和系统公开(公告)号：US08749576B2
公开(公告)日：2014-06-10
申请号：US11482669
申请日：2006-07-06
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T11/40
摘要： A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.
摘要翻译： 光栅化器级配置为实现图形管线的多个插值器。 光栅化器级包括多个可同时操作的低精度内插器，用于计算几何图元的像素的第一组像素参数和用于计算几何图元的像素的第二组像素参数的多个可同时操作的高精度内插器。 光栅化器级还包括耦合到内插器的输出机构，用于将计算出的像素参数路由到存储器阵列中。 参数可以可编程地分配给内插器，并且其结果可以可编程地分配给像素分组的部分。
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公开(公告)号：US08736620B2
公开(公告)日：2014-05-27
申请号：US10846201
申请日：2004-05-14
CPC分类号： G06T15/005
摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator. The status indicator is a kill bit is set to prevent logic components from clocking information for a payload portion of the pixel packet if the status indicator indicates the pixel packet payload does not contribute to the image display presentation while continuing to clock pixel packet sideband information.
摘要翻译： 本发明的像素处理系统和方法允许使用包括减少的栅极数量的浅图形管线来呈现复杂的三维图像，并且还有助于功率节省。 像素分组信息包括像素表面属性值在单个统一数据获取阶段检索。 在数据提取管线处，可以确定像素分组信息是否有助于图像显示呈现（例如，执行Z值的深度比较来确定像素是否被遮挡）。 像素分组状态指示符（例如，杀死比特）被设置在像素分组的边带部分中，并且像素分组被转发以根据像素分组状态指示符进行处理。 如果状态指示符指示像素分组有效载荷对图像显示呈现不起作用，同时继续对像素分组边带信息进行时钟处理，则状态指示符是设置为防止逻辑组件针对像素分组的有效载荷部分的时钟信息。
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公开(公告)号：US08711155B2
公开(公告)日：2014-04-29
申请号：US10845662
申请日：2004-05-14
CPC分类号： G06T15/40 , G06F9/3867 , G06F9/3869 , G06T15/005 , G06T2200/28
摘要： A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows. Any of a number of downstream pipestages may remove the occluded pixel information, and in response thereto, may notify a gatekeeper pipestage of the slack increase so that more pixels can be allowed into the pipeline.
摘要翻译： 一种像素处理系统和方法，其允许使用包括减少的门数和低功率操作的浅图形管线来呈现复杂的三维图像。 像素分组信息包括在单个统一数据获取阶段检索的像素表面属性值。 如果像素分组信息有助于图像显示呈现（例如，可以执行Z值的深度比较），则确定。 根据确定的结果处理像素分组信息处理。 如果像素表面属性值被遮挡，则像素表面属性值和像素分组信息从进一步处理中去除。 在一个示例性实现中，像素分组包括多个行，并且对于多个行来协调处理。 多个下游管道中的任何一个可以去除遮挡的像素信息，并且响应于此，可以通知网守管道的松弛增加，使得可以允许更多的像素进入流水线。
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公开(公告)号：US08441497B1
公开(公告)日：2013-05-14
申请号：US11890838
申请日：2007-08-07
CPC分类号： G06T15/005 , G06T15/20
摘要： Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware.
摘要翻译： 可以为图形原语访问顶点数据。 顶点数据包括基元的每个顶点的均匀坐标。 均匀坐标可用于确定通过原语区域归一化的透视校正重心坐标。 可以使用归一化的透视校正重心坐标来确定像素的属性的内插值。 这些操作可以使用在硬件中实现的加法器和乘法器执行。
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60.发明授权Method and system for implementing clamped z value interpolation in a raster stage of a graphics pipeline 有权用于在图形管线的光栅阶段中实现钳位的z值插值的方法和系统公开(公告)号：US08432394B1
公开(公告)日：2013-04-30
申请号：US10845992
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： A method of computing z parameters for pixels of a geometric primitive. The method includes the step of accessing the geometric primitive comprising a plurality of vertices, wherein each vertex comprises a plurality of associated parameters including a depth parameter, z. During rasterization of the geometric primitive, respective z values are interpolated for each pixel of the geometric primitive. Each z value is represented within a predefined numerical range which substantially corresponds to a depth range between a near plane and a far plane related to pixel rendering. During the interpolating, the z values are allowed to exceed the predefined numerical range and roll over within the predefined numerical range. A multi-bit indicator is used to indicate when a z value for a pixel is outside of the depth range.
摘要翻译： 一种计算几何图元像素的z参数的方法。 该方法包括访问包括多个顶点的几何图元的步骤，其中每个顶点包括多个相关参数，包括深度参数z。 在几何图元的光栅化期间，对于几何图元的每个像素插入相应的z值。 每个z值被表示在预定的数值范围内，其基本上对应于与像素渲染相关的近平面和远平面之间的深度范围。 在内插期间，允许z值超过预定义的数值范围，并在预定义的数值范围内翻转。 多位指示器用于指示像素的z值何时超出深度范围。
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