-
公开(公告)号：US09183607B1
公开(公告)日：2015-11-10
申请号：US11893431
申请日：2007-08-15
申请人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
发明人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
CPC分类号： G06T15/005 , G06T1/60 , G06T11/40
摘要： A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.
摘要翻译： 一种用于在图形处理器的图形管线中等待时间缓冲记分板的系统中的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元，并且对图形基元进行光栅化以生成与图形基元相关的多个像素。 存储的ID用于当像素被传送到图形处理器的后续阶段时考虑对于多个像素中的每一个的参数评估的启动。 缓冲器用于存储由后续阶段的多个像素中的每一个的参数评估产生的片段数据。 比较来自缓冲的ID和片段数据以确定它们是否彼此对应。 当ID和片段数据匹配并且片段数据被写入存储器时，对多个像素中的每一个的参数评估的完成进行了说明。
-
2.发明授权Reducing instruction execution passes of data groups through a data operation unit 有权通过数据操作单元减少数据组的指令执行次数公开(公告)号：US08856499B1
公开(公告)日：2014-10-07
申请号：US11893615
申请日：2007-08-15
申请人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
发明人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
CPC分类号： G06F9/3836 , G06F9/321 , G06F9/381 , G06F9/383
摘要： An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.
摘要翻译： 公开了一种装置。 该装置包括指令映射表，其包括多个指令计数和多个指令指针，每个指令指针与指令计数之一相对应。 每个指令指针标识下一个执行指令。 此外，每个指令计数指定从下一条指令开始执行的指令数。 该装置还具有数据操作单元，该数据操作单元适于接收数据组并适于在接收到的数据组上执行指令映射表的当前指令计数指定的指令数，该指令开始于由当前指令指针 在进行另一个数据组之前的指令映射表。
-
公开(公告)号：US08698819B1
公开(公告)日：2014-04-15
申请号：US11893439
申请日：2007-08-15
CPC分类号： G06T1/20
摘要： Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. One embodiment described a method of implementing software assisted shader merging for a graphics pipeline. The method involves accessing a first shader program in memory, and generating a first shader instruction from that program. This first instruction is loaded into an instruction table at a first location, indicated by an offset register. A second shader program in memory is then accessed, and used to generate a second shader instruction. The second shader instruction is loaded into the instruction table at a second location indicated by the offset register.
摘要翻译： 本文详细描述了用于编程图形管线和图形流水线内的模块的实施例。 一个实施例描述了为图形管线实现软件辅助着色器合并的方法。 该方法涉及访问存储器中的第一着色器程序，并从该程序生成第一着色器指令。 该第一指令被加载到由偏移寄存器指示的第一位置的指令表中。 然后访问存储器中的第二个着色器程序，并用于生成第二个着色器指令。 第二个着色器指令在由偏移寄存器指示的第二个位置加载到指令表中。
-
4.发明授权Program sequencer for generating indeterminant length shader programs for a graphics processor 有权用于为图形处理器生成不确定长度着色器程序的程序定序器公开(公告)号：US08659601B1
公开(公告)日：2014-02-25
申请号：US11893404
申请日：2007-08-15
CPC分类号： G06T15/005 , G06F9/5083 , G06T1/20
摘要： A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.
摘要翻译： 一种用于加载和执行不确定长度着色器程序的方法。 该方法包括访问GPU的图形存储器中的着色器程序的第一部分，并且将指令从第一部分加载到GPU的多个阶段以配置GPU用于程序执行。 然后根据来自第一部分的指令对一组像素进行处理。 在GPU的图形存储器中访问着色器程序的第二部分，并且来自第二部分的指令被加载到GPU的多个级中以配置GPU用于程序执行。 然后根据来自第二部分的指令对像素组进行处理。
-
公开(公告)号：US08594441B1
公开(公告)日：2013-11-26
申请号：US11520144
申请日：2006-09-12
CPC分类号： G06T9/00 , H04N1/646 , H04N19/124 , H04N19/136 , H04N19/186
摘要： Image-based data, such as a block of texel data, is accessed. The data includes sets of color component values. A luminance value is computed for each set of color components values, generating a range of luminance values. A first set and a second set of color component values that correspond to the minimum and maximum luminance values are selected from the sets of color component values. A third set of color component values can be mapped to an index that identifies how the color component values of the third set can be decoded using the color component values of the first and second sets. The index value is selected by determining where the luminance value for the third set lies in the range of luminance values.
摘要翻译： 访问基于图像的数据，例如一组纹素数据。 数据包括彩色分量值集合。 为每组颜色分量值计算亮度值，产生亮度值范围。 从颜色分量值的集合中选择对应于最小和最大亮度值的第一组和第二组颜色分量值。 可以将第三组颜色分量值映射到识别如何使用第一和第二组的颜色分量值来解码第三组的颜色分量值的索引。 通过确定第三组的亮度值位于亮度值的范围内来选择索引值。
-
公开(公告)号：US20120206447A1
公开(公告)日：2012-08-16
申请号：US13370184
申请日：2012-02-09
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
CPC分类号： G06T15/005
摘要： Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.
摘要翻译： 简而言之，根据一个或多个实施例，可重构3D图形处理器包括流水线配置管理器，光栅化器和耦合到三角形光栅器的存储器。 管线配置管理器能够将图形处理器配置为以直接光栅化模式或平铺模式操作以处理从处理单元接收的绘图命令序列。
-
7.发明申请公开(公告)号：US20110254848A1
公开(公告)日：2011-10-20
申请号：US11893499
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
摘要翻译： 图形处理器单元流水线中的算术逻辑级包括多个算术逻辑单元（ALU）和至少一个存储一组像素的像素数据的缓冲器。 每个时钟周期，缓冲存储一行一系列像素数据。 在将像素数据放置在缓冲器中之前，解串器反序列化像素数据行。 在缓冲器累积像素的所有像素数据行之后，可以由ALU操作像素的像素数据。
-
公开(公告)号：US08004522B1
公开(公告)日：2011-08-23
申请号：US11890839
申请日：2007-08-07
申请人： Michael J. M. Toksvig , Brian K. Cabral , Edward A. Hutchins , Gary C. King , Christopher D. S. Donham
发明人： Michael J. M. Toksvig , Brian K. Cabral , Edward A. Hutchins , Gary C. King , Christopher D. S. Donham
CPC分类号： G06T15/503
摘要： The boundary of a surface can be represented as a series of line segments. A number of polygons are successively superimposed onto the surface. The polygons utilize a common reference point and each of the polygons has an edge that coincides with one of the line segments. Coverage bits are associated with respective sample locations within a pixel. A value of a coverage bit is changed each time a sample location associated with the coverage bit is covered by one of the polygons. Final values of the coverage bits are buffered after all of the polygons have been processed. The values of the coverage bits can be used when the surface is subsequently rendered.
摘要翻译： 表面的边界可以表示为一系列线段。 多个多边形依次叠加在表面上。 多边形使用公共参考点，并且每个多边形具有与一个线段重合的边。 覆盖位与像素内的相应样本位置相关联。 每当与覆盖比特相关联的采样位置被多边形之一覆盖时，覆盖比特的值被改变。 所有覆盖位的最终值在所有的多边形都被处理后被缓冲。 当表面随后呈现时，可以使用覆盖位的值。
-
公开(公告)号：US07808512B1
公开(公告)日：2010-10-05
申请号：US11642276
申请日：2006-12-19
申请人： Edward A. Hutchins , Christopher D. S. Donham , Gary C. King , Michael J. M. Toksvig , Mark J. Kilgard
发明人： Edward A. Hutchins , Christopher D. S. Donham , Gary C. King , Michael J. M. Toksvig , Mark J. Kilgard
IPC分类号： G09G5/00
CPC分类号： G09G3/3611 , G09G5/225 , G09G2360/18
摘要： In a raster unit of a graphics processor, a method for bounding region accumulation for graphics rendering. The method includes receiving a plurality of graphics primitives for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitives to generate a plurality pixels related to the graphics primitives and a plurality of respective bounding regions related to the graphics primitives. Upon receiving an accumulation start command, the bounding regions are accumulated in an accumulation register. The accumulation continues until an accumulation stop command is received. The operation results in an accumulated bounding region. Access to the accumulated bounding region is enabled to facilitate a subsequent graphics rendering operation.
摘要翻译： 在图形处理器的光栅单元中，用于界定图形渲染的区域累积的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的多个图形基元，并且对图形基元进行光栅化以生成与图形基元相关的多个像素以及与图形基元相关的多个相应的边界区域。 在接收到累加开始命令时，边界区域被累积在累加寄存器中。 累积继续，直到接收到累加停止命令。 操作会导致累积的边界区域。 能够访问累积的边界区域以促进随后的图形绘制操作。
-
10.发明申请Shared readable and writeable global values in a graphics processor unit pipeline 有权在图形处理器单元管道中共享可读和可写的全局值公开(公告)号：US20090046103A1
公开(公告)日：2009-02-19
申请号：US11893622
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
CPC分类号： G09G5/363 , G06F9/30098 , G06F9/3879 , G06T1/20 , G06T15/005
摘要： An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.
摘要翻译： 图形处理器单元中的算术逻辑级包括算术逻辑单元（ALU）和全局寄存器。 这些寄存器包含一组像素的全局值。 可以从任何寄存器读取全局值，而不管由哪个像素由ALU操作。 然而，当写入ALU操作的结果时，根据像素数目，只有一些全局寄存器被写入候选。 因此，防止了数据的重写。
-
-
-
-
-
-
-
-
-
搜索结果
64 条记录 (耗时 0.066 秒)
