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公开(公告)号：US20130262772A1
公开(公告)日：2013-10-03
申请号：US13437537
申请日：2012-04-02
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F12/0802 , G06F2212/1041 , G06F2212/604
摘要： A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be allocated in the cache memory with a predefined initialization value. Subsequently, a portion of the cache memory is allocated to the assigned memory address region only after the data processing circuitry first attempts to perform a memory access on a memory address within the assigned memory address region. The allocated portion of the cache memory is then initialized with the predefined initialization value.
摘要翻译： 数据处理系统包括数据处理电路，高速缓冲存储器和存储器访问电路。 存储器访问电路用于以预定义的初始化值分配要在高速缓冲存储器中分配的存储器地址区域。 随后，仅在数据处理电路首先尝试对分配的存储器地址区域中的存储器地址执行存储器访问之后，将高速缓存存储器的一部分分配给分配的存储器地址区域。 然后用预定义的初始化值初始化高速缓冲存储器的分配部分。
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公开(公告)号：US20130077464A1
公开(公告)日：2013-03-28
申请号：US13245098
申请日：2011-09-26
CPC分类号： H04J13/12 , H04J13/0044
摘要： An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of first code bits in response to an index value and (ii) a plurality of first intermediate bits in response to the index value. The first code bits may be generated in parallel with the first intermediate bits. The second circuit may be configured to generate a plurality of second code bits in response to all of (i) the index value, (ii) the first code bits and (iii) the first intermediate bits. A combination of the first code bits and the second code bits generally forms one of a plurality of orthogonal codes.
摘要翻译： 公开了一种通常具有第一电路和第二电路的装置。 第一电路可以被配置为响应于索引值产生（i）多个第一码位，并且响应于索引值，产生多个第一中间位。 可以与第一中间位并行地生成第一码位。 第二电路可以被配置为响应于（i）索引值，（ii）第一码位和（iii）第一中间位的全部产生多个第二码位。 第一码位和第二码位的组合通常形成多个正交码中的一个。
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公开(公告)号：US20120324172A1
公开(公告)日：2012-12-20
申请号：US13163198
申请日：2011-06-17
IPC分类号： G06F12/08
CPC分类号： G06F12/121
摘要： An apparatus for performing data caching comprises at least one cache memory including multiple cache lines arranged into multiple segments, each segment having a subset of the cache lines associated therewith. The apparatus further includes a first plurality of counters, each of the counters being operative to track a number of active cache lines associated with a corresponding one of the segments. At least one controller included in the apparatus is operative to receive information relating to the number of active cache lines associated with a corresponding segment from the first plurality of counters and to implement a cache segment replacement policy for determining which of the segments to replace as a function of at least the information relating to the number of active cache lines associated with a corresponding segment.
摘要翻译： 用于执行数据高速缓存的装置包括至少一个高速缓存存储器，其包括布置成多个段的多个高速缓存行，每个段具有与其相关联的高速缓存行的子集。 该装置还包括第一多个计数器，每个计数器可操作以跟踪与相应的一个片段相关联的多个活动高速缓存线。 包括在装置中的至少一个控制器可操作以接收与来自第一多个计数器的与相应段相关联的有效高速缓存行的数量的信息，并且实现高速缓存段替换策略，用于确定将哪个段替换为 至少与与相应段相关联的活动高速缓存行的数量有关的信息的功能。
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公开(公告)号：US20120066456A1
公开(公告)日：2012-03-15
申请号：US12882515
申请日：2010-09-15
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： An apparatus having a first cache and a controller is disclosed. The first cache may be configured to assert a first signal after receiving given information in response to being ready to receive additional information. The controller may be configured to (i) fetch the given information from a memory to the first cache and (ii) prefetch first information in a direct memory access transfer from the memory to the first cache in response to the assertion of the first signal.
摘要翻译： 公开了具有第一高速缓存和控制器的装置。 第一缓存器可以被配置为响应于准备好接收附加信息而在接收给定信息之后断言第一信号。 控制器可以被配置为（i）从存储器获取给定信息到第一高速缓存，以及（ii）响应于第一信号的断言，从存储器到第一高速缓存的直接存储器访问传输中预取第一信息。
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