公开(公告)号：US11621051B2

公开(公告)日：2023-04-04

申请号：US17647793

申请日：2022-01-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS SA

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C11/34 ,  G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US11609851B2

公开(公告)日：2023-03-21

申请号：US17229161

申请日：2021-04-13

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Laurent Folliot ,  Emanuele Plebani ,  Mirko Falchetto

IPC: G06F12/06 ,  G06N3/04

Abstract: According to one aspect, a method for determining, for a memory allocation, placements in a memory area of data blocks generated by a neural network, comprises a development of an initial sequence of placements of blocks, each placement being selected from several possible placements, the initial sequence being defined as a candidate sequence, a development of at least one modified sequence of placements from a replacement of a given placement of the initial sequence by a memorized unselected placement, and, if the planned size of the memory area obtained by this modified sequence is less than that of the memory area of the candidate sequence, then this modified sequence becomes the candidate sequence, the placements of the blocks for the allocation being those of the placement sequence defined as a candidate sequence once each modified sequence has been developed.

公开(公告)号：US11604082B2

公开(公告)日：2023-03-14

申请号：US17171726

申请日：2021-02-09

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Laurent Beyly ,  Olivier Richard ,  Kenichi Oku

IPC: G01R27/26 ,  G01D5/24 ,  H03K17/96

Abstract: An embodiment of the present disclosure relates to a method of detection of a touch contact by a sensor including a first step of comparison of a voltage with a first voltage threshold; and a second step of comparison of the voltage with a second voltage threshold, the second step being implemented if the first voltage threshold has been reached within a duration shorter than a first duration threshold, the second voltage threshold being higher than the first voltage threshold.

公开(公告)号：US20230075227A1

公开(公告)日：2023-03-09

申请号：US17898288

申请日：2022-08-29

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (ROUSSET) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Emmanuel GRANDIN ,  Nabil SAFI ,  Maxime DORTEL ,  Laurent MEUNIER ,  Frederic RUELLE

IPC: G06F9/445 ,  G06F3/0482

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

公开(公告)号：US11593289B2

公开(公告)日：2023-02-28

申请号：US16516988

申请日：2019-07-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： François Cloute ,  Sandrine Lendre

IPC: G06F13/28

Abstract: A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.

公开(公告)号：US11568515B2

公开(公告)日：2023-01-31

申请号：US17361783

申请日：2021-06-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Julien Closs ,  Jean-Michel Delorme ,  Daniel Fauvarque ,  Laurent Folliot ,  Guillaume Legrain

IPC: G06N3/02 ,  G06T3/40 ,  G06N3/08

Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

公开(公告)号：US11552777B2

公开(公告)日：2023-01-10

申请号：US17457354

申请日：2021-12-02

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Onde ,  Diarmuid Emslie ,  Patrick Valdenaire

IPC: H04L7/00

Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

公开(公告)号：US11544480B2

公开(公告)日：2023-01-03

申请号：US17357182

申请日：2021-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Cordier ,  Anthony Tornambe

IPC: G06K7/10

Abstract: An operation of calibrating the object using a reference reader is performed, the calibration operation including an operation of placing the reference reader at various distances away from the object that correspond to various values of a parameter within the object that is representative of the intensity of the signal received by the object, and, for each distance, an operation of determining an internal phase-shift compensation in the object with respect to a nominal internal phase shift, making it possible to obtain a load modulation amplitude that is higher, in terms of absolute value, than a threshold, and an operation of storing a lookup table of the various values of the parameter and the corresponding internal phase-shift compensations.

公开(公告)号：US20220414268A1

公开(公告)日：2022-12-29

申请号：US17850497

申请日：2022-06-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Simon LANDRY ,  Yanis LINGE

IPC: G06F21/72

Abstract: The present disclosure relates to a method for protecting a first data item applied to a cryptographic algorithm, executed by a processor, wherein said algorithm is a per-round algorithm, with each round processing contents of first, second and third registers, the content of the second register being masked, during first parity rounds, by the content of a fourth register and the content of the third register being masked, during second parity rounds, by the content of a fifth register.

公开(公告)号：US11538941B2

公开(公告)日：2022-12-27

申请号：US17196226

申请日：2021-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L29/94 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L27/118

Abstract: An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.