公开(公告)号：US4802135A

公开(公告)日：1989-01-31

申请号：US902564

申请日：1986-09-02

申请人： Takashi Shinoda ,  Masamichi Ishihara

发明人： Takashi Shinoda ,  Masamichi Ishihara

IPC分类号： G11C11/34 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/408 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1021 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C8/18

摘要： A pseudo static RAM is provided which uses a one MOSFET dynamic RAM cell, in which two functions of a page mode and a static column mode are realized by using an address buffer having a function to transmit address signals fed from external terminals as they are and a latch function to latch the address signals fed from the external terminals in synchronism with predetermined control signals fed from the external terminals. The address buffer also has a multiplexer function to selectively incorporate the address signals from the external terminals and the address signals produced in the inside of the RAM so that the address buffer and an internal address signal generating circuit may be controlled by external control terminals to make possible the continuous access by the internal address signals.

摘要翻译： 提供了一种伪静态RAM，其使用一个MOSFET动态RAM单元，其中通过使用具有从外部端子原样馈送的地址信号的功能的地址缓冲器来实现页面模式和静态列模式的两个功能，以及 锁存功能，用于与从外部端子馈送的预定控制信号同步地锁存从外部端子馈送的地址信号。 地址缓冲器还具有多路复用功能，用于选择性地并入来自外部端子的地址信号和在RAM内部产生的地址信号，使得地址缓冲器和内部地址信号发生电路可以由外部控制端子控制， 可能通过内部地址信号的连续访问。