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公开(公告)号：US20200322549A1
公开(公告)日：2020-10-08
申请号：US16376426
申请日：2019-04-05
Applicant: Apple Inc.
Inventor： Sheng Lin , D. Amnon Silverstein
Abstract: Embodiments relate to image signal processors (ISP) that include binner circuits that down-sample an input image. An input image may include a plurality of pixels. The output image of the binner circuit may include a reduced number of pixels. The binner circuit may include a plurality of different operation modes. In a bin mode, the binner circuit may blend a subset of input pixel values to generate an output pixel quad. In a skip mode, the binner circuit may select one of the input pixel values as the output pixel pixel. The selection may be performed randomly to avoid aliasing. In a luminance mode, the binner circuit may take a weighted average of a subset of pixel values having different colors. In a color value mode, the binner circuit may select one of the colors in a subset of pixel values as an output pixel value.
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公开(公告)号：US20200084401A1
公开(公告)日：2020-03-12
申请号：US16593900
申请日：2019-10-04
Applicant: Apple Inc.
Inventor： Sheng Lin , D. Amnon Silverstein , David R. Pope , Suk Hwan Lim
Abstract: An image signal processor may include a pixel defect correction component that tracks defect history for frames captured by an image sensor and applies the history when identifying and correcting defective pixels in a frame. The component maintains a defect pixel location table that includes a defect confidence value for pixels of the image sensor. The component identifies defective pixels in a frame, for example by comparing each pixel's value to the values of its neighbor pixels. If a pixel is detected as defective, its defect confidence value may be incremented. Otherwise, the value may be decremented. If a pixel's defect confidence value is over a defect confidence threshold, the pixel is considered defective and thus may be corrected. If a pixel's defect confidence value is under the threshold, the pixel is considered not defective and thus may not be corrected even if the pixel was detected as defective.
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公开(公告)号：US10298863B2
公开(公告)日：2019-05-21
申请号：US14848276
申请日：2015-09-08
Applicant: Apple Inc.
Inventor： D. Amnon Silverstein , Sheng Lin , David R. Pope , Suk Hwan Lim
Abstract: Systems and methods for automatic lens flare compensation may include a non-uniformity detector configured to operate on pixel data for an image in an image sensor color pattern. The non-uniformity detector may detect a non-uniformity in the pixel data in a color channel of the image sensor color pattern. The non-uniformity detector may generate output including location and magnitude values of the non-uniformity. A lens flare detector may determine, based at least on the location and magnitude values, whether the output of the non-uniformity detector corresponds to a lens flare in the image. In some embodiments, the lens flare detector may generate, in response to determining that the output corresponds to the lens flare, a representative map of the lens flare. A lens flare corrector may determine one or more pixel data correction values corresponding to the lens flare and apply the pixel data correction values to the pixel data.
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公开(公告)号：US09787922B2
公开(公告)日：2017-10-10
申请号：US14841345
申请日：2015-08-31
Applicant: Apple Inc.
Inventor： Sheng Lin , Suk Hwan Lim
Abstract: An image signal processor may include a sensor interface that includes a pixel defect preprocessing (PDP) component that performs an initial adjustment of pixel values for patterned defect pixels in raw pixel data captured by an image sensor. To adjust a patterned defect pixel, the PDP component may apply an interpolation technique to values in a gain lookup table according to the pixel's location in the image frame to determine the gain value for the pixel, and then apply the gain value to the pixel. The PDP component may provide the raw pixel data with the adjusted patterned defect pixels to two or more other modules for additional processing. The other modules may include an image processing pipeline that may detect other defective pixels in the raw pixel data and correct the patterned defect pixels and the other defective pixels, for example using a weighted combination of neighboring pixels.
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55.发明申请CORRECTING PIXEL DEFECTS BASED ON DEFECT HISTORY IN AN IMAGE PROCESSING PIPELINE 审中-公开基于图像处理管道中的缺陷历史校正像素缺陷公开(公告)号：US20170070692A1
公开(公告)日：2017-03-09
申请号：US14845659
申请日：2015-09-04
Applicant: Apple Inc.
Inventor： Sheng Lin , D. Amnon Silverstein , David R. Pope , Suk Hwan Lim
Abstract: An image signal processor may include a pixel defect correction component that tracks defect history for frames captured by an image sensor and applies the history when identifying and correcting defective pixels in a frame. The component maintains a defect pixel location table that includes a defect confidence value for pixels of the image sensor. The component identifies defective pixels in a frame, for example by comparing each pixel's value to the values of its neighbor pixels. If a pixel is detected as defective, its defect confidence value may be incremented. Otherwise, the value may be decremented. If a pixel's defect confidence value is over a defect confidence threshold, the pixel is considered defective and thus may be corrected. If a pixel's defect confidence value is under the threshold, the pixel is considered not defective and thus may not be corrected even if the pixel was detected as defective.
Abstract translation: 图像信号处理器可以包括跟踪由图像传感器捕获的帧的缺陷历史的像素缺陷校正组件，并且在识别和校正帧中的缺陷像素时应用历史。 该组件保持缺陷像素位置表，其包括图像传感器的像素的缺陷置信度值。 组件识别帧中的缺陷像素，例如通过将每个像素的值与其相邻像素的值进行比较。 如果像素被检测为缺陷，则其缺陷置信度值可以增加。 否则，该值可能会减少。 如果像素的缺陷置信度值超过缺陷置信度阈值，则该像素被认为是有缺陷的，因此可被校正。 如果像素的缺陷置信度值低于阈值，则认为像素不是有缺陷的，因此即使像素被检测为有缺陷，也可能不被校正。
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Patent Agency Ranking
公开(公告)号：US20160110843A1
公开(公告)日：2016-04-21
申请号：US14977384
申请日：2015-12-21
Applicant: Apple Inc.
Inventor： Christopher L. Mills , Sheng Lin , David R. Pope , D. Amnon Silverstein , Suk Hwan Lim
CPC classification number: H04N9/04511 , G06T3/4015 , H04N5/2628 , H04N9/07 , H04N9/646 , H04N2209/046
Abstract: An input rescale module that performs cross-color correlated downscaling of sensor data in the horizontal and vertical dimensions. The module may perform a first-pass demosaic of sensor data, apply horizontal and vertical scalers to resample and downsize the data in the horizontal and vertical dimensions, and then remosaic the data to provide horizontally and vertically downscaled sensor data as output for additional image processing. The module may, for example, act as a front end scaler for an image signal processor (ISP). The demosaic performed by the module may be a relatively simple demosaic, for example a demosaic function that works on 3×3 blocks of pixels. The front end of module may receive and process sensor data at two pixels per clock (ppc); the horizontal filter component reduces the sensor data down to one ppc for downstream components of the input rescale module and for the ISP pipeline.
Abstract translation: 在水平和垂直维度上执行传感器数据的交叉色相关缩小的输入重定标模块。 模块可以执行传感器数据的第一遍去马赛克，应用水平和垂直缩放器对水平和垂直尺寸的数据进行重新取样和缩小，然后重新绘制数据，以提供水平和垂直缩小的传感器数据作为附加图像处理的输出 。 该模块可以例如用作图像信号处理器（ISP）的前端缩放器。 由模块执行的去镶嵌可以是相对简单的去马赛克，例如在3×3像素块上工作的去马赛克功能。 模块的前端可以以每个时钟两个像素（ppc）接收和处理传感器数据; 水平滤波器组件将传感器数据减少到输入重定标模块的下游组件和ISP管线的一ppc。
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公开(公告)号：US20240029198A1
公开(公告)日：2024-01-25
申请号：US18230560
申请日：2023-08-04
Applicant: Apple Inc.
Inventor： Chihsin WU , David R. Pope , Sheng Lin , Amnon D. Silverstein
CPC classification number: G06T3/4007 , H04N23/88
Abstract: A foveated down sampling and correction (FDS-C) circuit for combined down sampling and correction of chromatic aberrations in images. The FDS-C circuit performs down sampling and interpolation of pixel values of a first subset of pixels of a color in a raw image using down sampling scale factors and first interpolation coefficients to generate first corrected pixel values for pixels of the color in a first corrected version of the raw image. The FDS-C circuit further performs interpolation of pixel values of a second subset of the pixels in the first corrected version using second interpolation coefficients to generate second corrected pixel values for pixels of the color in a second corrected version of the raw image. Pixels in the first subset are arranged in a first direction, pixels in the second subset are arranged in a second direction, and the down sampling scale factors vary along the first direction.
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公开(公告)号：US20230232122A1
公开(公告)日：2023-07-20
申请号：US17578055
申请日：2022-01-18
Applicant: Apple Inc.
Inventor： Sarvesh Swami , David R. Pope , Sheng Lin
CPC classification number: H04N9/04515 , H04N9/67 , H04N5/23229
Abstract: Embodiments relate to a multi-mode demosaicing circuit able to receive and demosaic image data in a different raw image formats, such as Bayer raw image format and Quad Bayer raw image format. The multi-mode demosaicing circuit comprises different circuitry for demosaicing different image formats that access a shared working memory. In addition, the multi-mode demosaicing circuit shares memory with a post-processing and scaling circuit configured to perform subsequent post-processing and/or scaling of the demosaiced image data, in which the operations of the post-processing and scaling circuit are modified based on the original raw image format of the demosaiced image data to use different amounts of the shared memory, to compensate for additional memory utilized by the multi-mode demosaicing circuit when demosaicing certain types of image data.
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公开(公告)号：US20230230200A1
公开(公告)日：2023-07-20
申请号：US17578195
申请日：2022-01-18
Applicant: Apple Inc.
Inventor： Sarvesh Swami , David R. Pope , Sheng Lin
CPC classification number: G06T3/4015 , G06T5/002 , G06T5/50 , G06T2207/20212
Abstract: Embodiments relate to a front-end scaler circuit configured to receive and process demosaiced image data in different modes depending on if the demosaiced image data was demosaiced from Bayer or Quad Bayer raw image data. The front-end scaler circuit shares memory with a demosaicing circuit, and is configured to perform different operations that use different amounts of the shared memory based on the original image format of the demosaiced image data being processed, to compensate for additional memory utilized by the demosaicing circuit when demosaicing certain types of image data. For example, when processing image data demosaiced from Quad Bayer image data, the front-end scaler circuit discards a portion of the chrominance component data for the received image data before performing chromatic suppression, compared to when processing image data demosaiced from Bayer image data.
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公开(公告)号：US11689826B2
公开(公告)日：2023-06-27
申请号：US17377308
申请日：2021-07-15
Applicant: Apple Inc.
Inventor： Guy Cote , D. Amnon Silverstein , Suk Hwan Lim , Sheng Lin , Haitao Guo
CPC classification number: H04N25/67
Abstract: The present disclosure generally relates to systems and methods for image data processing. In certain embodiments, an image processing pipeline may be configured to receive a frame of the image data having a plurality of pixels acquired using a digital image sensor. The image processing pipeline may then be configured to determine a first plurality of correction factors that may correct each pixel in the plurality of pixels for fixed pattern noise. The first plurality of correction factors may be determined based at least in part on fixed pattern noise statistics that correspond to the frame of the image data. After determining the first plurality of correction factors, the image processing pipeline may be configured to configured to apply the first plurality of correction factors to the plurality of pixels, thereby reducing the fixed pattern noise present in the plurality of pixels.
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