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61 条记录 (耗时 0.028 秒)

    Method and structure for managing large counter arrays
    52.
    发明授权
    Method and structure for managing large counter arrays 有权
    管理大型计数器阵列的方法和结构

    公开(公告)号：US06658584B1

    公开(公告)日：2003-12-02

    申请号：US09656556

    申请日：2000-09-06

    申请人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    发明人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    IPC分类号： G06F104

    CPC分类号： G06F1/04

    摘要： A method and structure for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex, which processor complex has at least one processor which processes multiple groups of data in a multiplicity of ways, is provided. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event. A counter manager is provided which communicates with said at least one processor through its associated coprocessors and receives the parameters of each event generated from the at least one processor. The counter manager, utilizing the table and the parameters information from the at least one processor determines the unique physical address location associated with the event, reads the data from the unique address, modifies the read data according to the instructions and writes the modified data to the determined address. The invention also contemplates reading the information which has been stored for statistical evaluation at the address without modifying the stored information.

    摘要翻译： 提供了一种用于计数和存储在处理器复合体中发生的多个事件中的每一个的出现次数的方法和结构，该处理器复合体具有以多种方式处理多组数据的至少一个处理器。 该结构包括多个存储设备，每个存储设备包括用于存储每个事件的计数信息的多个存储器存储阵列，哪些阵列被划分成每个存储器阵列中的多个单独可寻址的存储器地址组。 至少一个计数器元件与每个存储器阵列相关联。 提供了一个包含信息的表，其中包括每个数组中的参考点，以唯一地定义每个存储器阵列的结构和位置。 至少一个处理器为每个事件生成多个参数以唯一地识别该事件。 提供了一种计数器管理器，其经由其相关联的协处理器与所述至少一个处理器进行通信，并接收从至少一个处理器生成的每个事件的参数。 计数器管理器利用来自至少一个处理器的表和参数信息确定与事件相关联的唯一物理地址位置，从唯一地址读取数据，根据指令修改读取的数据，并将修改的数据写入 确定的地址。 本发明还考虑在不修改存储的信息的情况下读取已经存储的用于统计评估的地址的信息。

    System and method for delayed increment of a counter
    56.
    发明授权
    System and method for delayed increment of a counter 失效
    计数器延迟增量的系统和方法

    公开(公告)号：US06996737B2

    公开(公告)日：2006-02-07

    申请号：US10680521

    申请日：2003-10-07

    申请人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    发明人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    IPC分类号： G06F1/04

    CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

    摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

    摘要翻译： 提供了用于执行延迟计数器增量的方法和结构。 该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。 在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。 因此，计数器递增指令被改变。 延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。 在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。 这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

    LAN switch with distributed copy function
    57.
    发明授权
    LAN switch with distributed copy function 失效
    局域网交换机具有分布式复制功能

    公开(公告)号：US5793764A

    公开(公告)日：1998-08-11

    申请号：US614221

    申请日：1996-03-12

    申请人： Robert William Bartoldus ,  Brian Mitchell Bass ,  Kenneth H. Potter, Jr. ,  William Craig Troop

    发明人： Robert William Bartoldus ,  Brian Mitchell Bass ,  Kenneth H. Potter, Jr. ,  William Craig Troop

    IPC分类号： H04L12/46 ,  H04L12/44 ,  H04L12/56

    CPC分类号： H04L45/742 ,  H04L49/351 ,  H04L49/3027 ,  H04L49/40

    摘要： A LAN switching system includes an Address Match Control line which can be set (activated) and is monitored by each port adapter card. If a port adapter card recognizes an address on the switch fabric, the adapter card copies the frame with the address and activates the Address match Control line. The set Address Match Control line causes the remaining port adapter cards to stop searching for a match. If the Address Match Control line is not set, the frame can be copied by all port adapters which are configured to do so.

    摘要翻译： LAN交换系统包括地址匹配控制线，可以设置（激活）并由每个端口适配卡监视。 如果端口适配器卡识别交换机结构上的地址，则适配器卡将复制带有该地址的帧，并激活“地址匹配控制”行。 设置的地址匹配控制行使剩余的端口适配器卡停止搜索匹配。 如果未设置地址匹配控制行，则可以通过配置为这样做的所有端口适配器复制该帧。

    Method and Apparatus for Concurrent and Stateful Decompression of Multiple Compressed Data Streams
    58.
    发明申请
    Method and Apparatus for Concurrent and Stateful Decompression of Multiple Compressed Data Streams 失效
    用于多个压缩数据流的并发和有状态解压缩的方法和装置

    公开(公告)号：US20100020825A1

    公开(公告)日：2010-01-28

    申请号：US12177440

    申请日：2008-07-22

    申请人： Brian Mitchell Bass ,  Giora Biran ,  Hubertus Franke ,  Hao Yu

    发明人： Brian Mitchell Bass ,  Giora Biran ,  Hubertus Franke ,  Hao Yu

    IPC分类号： H04L29/02

    CPC分类号： H04L69/04 ,  G06F2221/2105 ,  H04L63/0227

    摘要： A method for decompressing multiple data streams includes receiving a packet of data of a compressed data stream, directing the received packet to a selected one of a plurality of decompression functional units within a hardware-based decompression accelerator unit, obtaining decompression state information pertaining to the compressed data stream, and decompressing the received packet using the obtained decompression state information.

    摘要翻译： 用于解压缩多个数据流的方法包括：接收压缩数据流的数据分组，将接收的分组引导到基于硬件的解压缩加速器单元内的多个解压缩功能单元中的选定的一个，获得与 压缩数据流，并使用获得的解压缩状态信息对接收的分组进行解压缩。

    System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined
    59.
    发明授权
    System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined 失效
    用于延迟在处理器中发生的多个事件的发生的计数的系统，直到已经确定了事件的处理

    公开(公告)号：US06701447B1

    公开(公告)日：2004-03-02

    申请号：US09656547

    申请日：2000-09-06

    申请人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    发明人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    IPC分类号： G06F104

    CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

    摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

    摘要翻译： 提供了用于执行延迟计数器增量的方法和结构。 该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。 在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。 因此，计数器递增指令被改变。 延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。 在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。 这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

    Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system
    60.
    发明授权
    Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system 失效
    用于在计算机系统中实现非中断活动插入和移除功能卡的方法和系统

    公开(公告)号：US6041375A

    公开(公告)日：2000-03-21

    申请号：US321688

    申请日：1999-05-28

    申请人： Brian Mitchell Bass ,  James Allison Hubbard ,  Price Ward Oman ,  Frank J. Pita

    发明人： Brian Mitchell Bass ,  James Allison Hubbard ,  Price Ward Oman ,  Frank J. Pita

    IPC分类号： G06F3/00 ,  G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/4081

    摘要： Method and system for controlling the state of a system bus during live insertion and removal of a pluggable feature card (FC) by driving control signals, which are transferred over the system bus, to an active signal level, or by driving down level active control signals to a low signal level near ground level. By this mechanism, the system bus becomes immune to signal disturbances and thereby allows pluggable units to be live inserted and removed without causing adverse effects to the system such as a system reset or compromise of data integrity. During live insertion or removal, a Live Insertion Bus Controller (LIBC) acquires access to the system bus through its interface with a System Bus Controller (SBC), after it has been signalled by a live insertion mechanism associated with the FC that the FC is in the process of being live inserted or removed. After system bus access has been acquired by the LIBC and the LIBC has taken over the control of the system bus, it drives a subset of the system bus set of control signals to a state that is immune from insertion/removal signal disturbance. In parallel, the LIBC effects suspension of running timeout and watchdog operations currently being performed by the SBC. When the LIBC is informed that the insertion process has been completed, the SBC again acquires control of the system bus. The same procedural steps are performed in case of removal of an FC.

    摘要翻译： 用于通过将通过系统总线传送的控制信号驱动到活动信号电平或通过驱动下降电平主动控制来实时插入和移除可插拔特征卡（FC）来控制系统总线的状态的方法和系统 信号到地平面附近的低信号电平。 通过这种机制，系统总线免受信号干扰的影响，从而允许可插拔单元被实时插入和移除，而不会对系统造成不利影响，例如系统复位或泄漏数据完整性。 在实时插入或删除过程中，实时插入总线控制器（LIBC）通过与系统总线控制器（SBC）的接口获取对系统总线的访问，在通过与FC相关的活动插入机制发出信号后，FC为FC 在被插入或移除的过程中。 在LIBC已经获得系统总线访问之后，LIBC已经接管了系统总线的控制，它将系统总线控制信号的一部分驱动到不受插入/移除信号干扰的状态。 同时，LIBC会影响SBC正在执行的运行超时和看门狗操作的暂停。 当LIBC被告知插入过程已经完成时，SBC再次获得对系统总线的控制。 在删除FC的情况下执行相同的程序步骤。