Server side filtering and sorting with field level security
    51.
    发明授权
    Server side filtering and sorting with field level security 有权
    服务器端过滤和排序与现场级安全性

    公开(公告)号:US07599934B2

    公开(公告)日:2009-10-06

    申请号:US11235784

    申请日:2005-09-27

    IPC分类号: G06F17/30 H04L9/00

    摘要: A project management system is enabled to implement filtering, sorting, and field level security for data associated with managed projects. A filter for field selection is prepared by a project client application and forwarded to a project server. The server generates an access attribute table based the user permissions that may be set for each field within the managed projects. Upon retrieving the selected fields from project database, the project server builds a secured list of fields. A data set to be provided to the project client is prepared by removing the fields for which the user lacks the requisite access permission prior to sorting the data. The removed data may be used for user-transparent computations within the project server, but guarded from client applications.

    摘要翻译: 项目管理系统能够实现与被管理项目相关的数据的过滤,排序和现场级安全性。 用于现场选择的过滤器由项目客户端应用程序准备并转发到项目服务器。 服务器根据受管理项目中每个字段可能设置的用户权限生成访问属性表。 从项目数据库检索所选字段后,项目服务器构建一个安全的字段列表。 通过在排序数据之前,删除用户缺少必要的访问许可的字段来准备提供给项目客户端的数据集。 删除的数据可以用于项目服务器内的用户透明计算,但可以从客户端应用程序中保护。

    Server queuing system and method
    52.
    发明授权
    Server queuing system and method 失效
    服务器排队系统和方法

    公开(公告)号:US07502843B2

    公开(公告)日:2009-03-10

    申请号:US11026501

    申请日:2004-12-30

    IPC分类号: G06F15/173

    摘要: A queuing server is used for reliable message transport, where one subsystem desires to execute one or more ordered operations asynchronously. Messages are sent to the queue in groups, which may have one or more messages. Messages within a particular group are processed in a predetermined order. Optionally, groups of messages can marked as correlated such that all groups within a particular correlation can be processed in a predetermined order. A message can be stored in a SQL database table until processing of that message is complete. The receiving side of the message system can be scaled across multiple machines and/or across available resources of any given machine. The system can handle “disaster” scenarios on both the sending side (i.e. the sending machine crashes in the middle of sending a group), and the receiving side (i.e., a power failure causes a reboot in at least one of the receiving machines).

    摘要翻译: 排队服务器用于可靠的消息传输,其中一个子系统希望以异步方式执行一个或多个有序操作。 消息以组的形式发送到队列,可能有一个或多个消息。 以预定顺序处理特定组内的消息。 可选地,消息组可被标记为相关联,使得可以以预定顺序处理特定相关中的所有组。 消息可以存储在SQL数据库表中,直到该消息的处理完成为止。 消息系统的接收端可以跨多个机器和/或任何给定机器的可用资源进行扩展。 系统可以处理发送方的“灾难”情况(即,发送机在发送组中间时发生故障),接收方(即,电源故障导致至少一个接收机中的重启) 。

    HIGH-VOLTAGE MOS TRANSISTOR DEVICE
    53.
    发明申请
    HIGH-VOLTAGE MOS TRANSISTOR DEVICE 有权
    高压MOS晶体管器件

    公开(公告)号:US20090039425A1

    公开(公告)日:2009-02-12

    申请号:US11836788

    申请日:2007-08-10

    IPC分类号: H01L29/78

    摘要: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.

    摘要翻译: 公开了一种HV MOS晶体管器件,其具有衬底,栅极,源极,漏极,设置在衬底中的第一导电类型的第一离子阱以及设置在衬底上的多个场板。 HV MOS晶体管器件还具有位于第一离子阱中的第二导电类型的第一掺杂区域。 因此,形成第一离子阱和第一掺杂区之间的第一界面和第二界面,并且第一界面和第二界面分别位于漏极和源附近。 此外,第一接口位于相应的场板下方以产生平滑的场分布并增加HV晶体管器件的击穿电压。

    SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME
    54.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME 审中-公开
    半导体器件及其操作方法

    公开(公告)号:US20080093700A1

    公开(公告)日:2008-04-24

    申请号:US11551248

    申请日:2006-10-20

    申请人: Chih-Jen Huang

    发明人: Chih-Jen Huang

    IPC分类号: H01L29/00

    摘要: A method for operating a semiconductor device is described, the semiconductor device including a high-voltage device and a control circuit coupled to each other on a single chip and the high-voltage device including a source, a drain and a gate. This method applies a drain voltage of about 20V or higher to the drain while the gate and the source are floated, such that the high-voltage device self-turns on to produce a current from the drain to the source charging up the source and forming a source voltage. The source voltage serves as a power source of the control circuit, and the control circuit is driven when the source voltage is higher than the threshold voltage thereof.

    摘要翻译: 描述了一种用于操作半导体器件的方法,该半导体器件包括在单个芯片上彼此耦合的高压器件和控制电路,以及包括源极,漏极和栅极的高压器件。 该方法在栅极和源极浮置时向漏极施加约20V或更高的漏极电压,使得高压器件自身导通以产生从漏极到源极充电源的电流并形成 源电压。 源电压用作控制电路的电源,并且当电源电压高于其阈值电压时驱动控制电路。

    Method of manufacturing a high voltage using a latid process for forming a LDD
    55.
    发明授权
    Method of manufacturing a high voltage using a latid process for forming a LDD 失效
    使用用于形成LDD的间隙工艺来制造高电压的方法

    公开(公告)号:US06429082B1

    公开(公告)日:2002-08-06

    申请号:US09684118

    申请日:2000-10-06

    IPC分类号: H01L21265

    摘要: A method of manufacturing a high voltage device is described. A well region is formed within a substrate of a high voltage device region. A gate structure is made up of a gate oxide layer, a gate and an optional cap layer that are sequentially formed upon the well. Subsequently, using the gate structure as a mask, a large tilt angle light doping process is performed on the well of the high voltage device region of the well, thereby forming a lightly doped source and drain region. Thereupon, a optional thermal drive-in procedure is performed. Next, a spacer is formed on the side of the gate structure. Using the spacer and the gate structure as a mask, a heavy doping self-aligned ion implantation process is performed on the active region of the well, thereby forming a heavily doped source and drain region.

    摘要翻译: 对高压装置的制造方法进行说明。 在高电压器件区域的衬底内形成阱区。 栅极结构由顺序地形成在阱上的栅极氧化物层,栅极和可选的覆盖层构成。 随后,使用栅极结构作为掩模,对阱的高压器件区域的阱执行大的倾斜角度的掺杂工艺,从而形成轻掺杂的源极和漏极区域。 因此,执行可选的热驱动程序。 接下来,在栅极结构侧形成间隔物。 使用间隔物和栅极结构作为掩模,对阱的有源区域进行重掺杂自对准离子注入工艺,由此形成重掺杂的源极和漏极区域。

    Electrically erasable non-volatile memory
    56.
    发明授权
    Electrically erasable non-volatile memory 有权
    电可擦除非易失性存储器

    公开(公告)号:US06255172B1

    公开(公告)日:2001-07-03

    申请号:US09567918

    申请日:2000-05-10

    IPC分类号: H01L218247

    CPC分类号: H01L29/66825 H01L21/28273

    摘要: A method of manufacturing an electrically erasable non-volatile memory is suitable for use on a substrate. The method includes the following steps. First, a tunnel oxide layer is formed on the substrate. A floating gate and a silicon oxide layer/silicon nitride/silicon oxide layer is formed in order on the tunnel oxide layer. Next, a first oxide layer and a silicon nitride spacer are formed in order on the sidewalls of the floating gate. A second oxide layer is formed along the surface of the above entire structure. A third oxide layer is formed on the substrate on both sides of the silicon nitride spacer by oxidation. A patterned conductive layer on the substrate to serve as a control gate and a select transistor gate is formed above the substrate. Using the select transistor gate as a mask, the exposed part of the third oxide layer is removed to make the residual third oxide layer serve as a gate oxide layer of the select transistor. Finally, ion implantation is performed on the substrate to form source and drain regions.

    摘要翻译: 制造电可擦除非易失性存储器的方法适用于基板。 该方法包括以下步骤。 首先,在基板上形成隧道氧化层。 在隧道氧化物层上依次形成浮置栅极和氧化硅层/氮化硅/氧化硅层。 接下来,在浮栅的侧壁上依次形成第一氧化物层和氮化硅间隔物。 沿着上述整个结构的表面形成第二氧化物层。 通过氧化在氮化硅间隔物的两侧的基板上形成第三氧化物层。 在衬底上形成用作控制栅极和选择晶体管栅极的图案化导电层。 使用选择晶体管栅极作为掩模,去除第三氧化物层的暴露部分,使剩余的第三氧化物层用作选择晶体管的栅极氧化物层。 最后,在衬底上进行离子注入以形成源区和漏区。