摘要:
A project management system is enabled to implement filtering, sorting, and field level security for data associated with managed projects. A filter for field selection is prepared by a project client application and forwarded to a project server. The server generates an access attribute table based the user permissions that may be set for each field within the managed projects. Upon retrieving the selected fields from project database, the project server builds a secured list of fields. A data set to be provided to the project client is prepared by removing the fields for which the user lacks the requisite access permission prior to sorting the data. The removed data may be used for user-transparent computations within the project server, but guarded from client applications.
摘要:
A queuing server is used for reliable message transport, where one subsystem desires to execute one or more ordered operations asynchronously. Messages are sent to the queue in groups, which may have one or more messages. Messages within a particular group are processed in a predetermined order. Optionally, groups of messages can marked as correlated such that all groups within a particular correlation can be processed in a predetermined order. A message can be stored in a SQL database table until processing of that message is complete. The receiving side of the message system can be scaled across multiple machines and/or across available resources of any given machine. The system can handle “disaster” scenarios on both the sending side (i.e. the sending machine crashes in the middle of sending a group), and the receiving side (i.e., a power failure causes a reboot in at least one of the receiving machines).
摘要:
A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.
摘要:
A method for operating a semiconductor device is described, the semiconductor device including a high-voltage device and a control circuit coupled to each other on a single chip and the high-voltage device including a source, a drain and a gate. This method applies a drain voltage of about 20V or higher to the drain while the gate and the source are floated, such that the high-voltage device self-turns on to produce a current from the drain to the source charging up the source and forming a source voltage. The source voltage serves as a power source of the control circuit, and the control circuit is driven when the source voltage is higher than the threshold voltage thereof.
摘要:
A method of manufacturing a high voltage device is described. A well region is formed within a substrate of a high voltage device region. A gate structure is made up of a gate oxide layer, a gate and an optional cap layer that are sequentially formed upon the well. Subsequently, using the gate structure as a mask, a large tilt angle light doping process is performed on the well of the high voltage device region of the well, thereby forming a lightly doped source and drain region. Thereupon, a optional thermal drive-in procedure is performed. Next, a spacer is formed on the side of the gate structure. Using the spacer and the gate structure as a mask, a heavy doping self-aligned ion implantation process is performed on the active region of the well, thereby forming a heavily doped source and drain region.
摘要:
A method of manufacturing an electrically erasable non-volatile memory is suitable for use on a substrate. The method includes the following steps. First, a tunnel oxide layer is formed on the substrate. A floating gate and a silicon oxide layer/silicon nitride/silicon oxide layer is formed in order on the tunnel oxide layer. Next, a first oxide layer and a silicon nitride spacer are formed in order on the sidewalls of the floating gate. A second oxide layer is formed along the surface of the above entire structure. A third oxide layer is formed on the substrate on both sides of the silicon nitride spacer by oxidation. A patterned conductive layer on the substrate to serve as a control gate and a select transistor gate is formed above the substrate. Using the select transistor gate as a mask, the exposed part of the third oxide layer is removed to make the residual third oxide layer serve as a gate oxide layer of the select transistor. Finally, ion implantation is performed on the substrate to form source and drain regions.