公开(公告)号：US5766967A

公开(公告)日：1998-06-16

申请号：US726952

申请日：1996-10-07

申请人： Yeong-Lin Lai ,  Hung-Ping D. Yang ,  Chun-Yen Chang ,  Edward Y. Chang ,  Kazumitsu Nakamura ,  Rico Chang

发明人： Yeong-Lin Lai ,  Hung-Ping D. Yang ,  Chun-Yen Chang ,  Edward Y. Chang ,  Kazumitsu Nakamura ,  Rico Chang

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L21/8232

CPC分类号： H01L29/66863 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/66462 ,  Y10S438/951

摘要： A method for fabricating submicron T-shaped gates for the field-effect transistors disclosed, which can be accomplished by using a tri-layer positive photoresist with a single electron beam exposure and a single development step. Therefore, the cost can be reduced and the yield can be raised for fabricating high speed field-effect transistors. The method comprises the steps of: (i) sequentially spinning coating a first photoresist layer, a second photoresist layer and a third photoresist layer on the top of epitaxial layers, wherein the second photoresist layer is thicker than the third photoresist layer, and the third photoresist layer is not thicker than the first photoresist layer, the viscosity of the second photoresist layer is larger than that of the first and third photoresist layers, and the electron beam sensitivity of the second photoresist layer is larger than that of the first and the third photoresist layers; (ii) exposing all the gate stripe region of the photoresist layers by a single electron beam exposure; (iii) using a developer to develop all the exposed positions of the three photoresist layers by a single development step, so that a T-shaped opening is formed; (iv) etching and removing a contact layer of the epitaxial layers under the T-shaped opening; (v) evaporating gate metal layers to cover the third photoresist layer and to fill the T-shaped opening; (vi) removing the photoresist layers to lift off the evaporated metal layers so that the submicron T-shaped gate is obtained.

摘要翻译： 公开了用于制造用于场效应晶体管的亚微米T形栅极的方法，其可以通过使用具有单电子束曝光的三层正性光致抗蚀剂和单一显影步骤来实现。 因此，可以降低成本并且可以提高用于制造高速场效应晶体管的产量。 该方法包括以下步骤：（i）在外延层的顶部上依次纺丝涂覆第一光致抗蚀剂层，第二光致抗蚀剂层和第三光致抗蚀剂层，其中第二光致抗蚀剂层比第三光致抗蚀剂层厚， 光致抗蚀剂层不比第一光致抗蚀剂层厚，第二光致抗蚀剂层的粘度大于第一和第三光致抗蚀剂层的粘度，并且第二光致抗蚀剂层的电子束灵敏度大于第一和第三光致抗蚀剂层的电子束灵敏度 光阻层; （ii）通过单个电子束曝光曝光光致抗蚀剂层的所有栅条纹区域; （iii）通过单个显影步骤使用显影剂显影三个光致抗蚀剂层的所有曝光位置，从而形成T形开口; （iv）在T形开口下蚀刻除去外延层的接触层; （v）蒸发栅极金属层以覆盖第三光致抗蚀剂层并填充T形开口; （vi）去除光致抗蚀剂层以剥离蒸发的金属层，从而获得亚微米T形门。

公开(公告)号：US5554985A

公开(公告)日：1996-09-10

申请号：US490310

申请日：1995-06-14

申请人： Chun-Yen Chang

发明人： Chun-Yen Chang

IPC分类号： H03M11/20 ,  H03K17/94

CPC分类号： H03M11/20

摘要： A scanning method of keypad architectures utilizing power pin V.sub.DD and ground pin GND of an integrated circuit device is disclosed. The integrated circuit device has a number of row pins and column pins, a power pin and a ground pin, and a number of pins for other functions of the integrated circuit device. The row and column pins, power pin and ground pin of the integrated circuit device are connected to respective connections of a keyswitch matrix, which has a plurality of row connections and column connections. The keyswitch matrix of the scanning apparatus has a first one of the row connections connected to the power pin. The keyswitch matrix of the scanning apparatus has a second one of the row connection connected to the ground pin. Each of the other row pins is connected respectively to corresponding one of the row connections. Each of the column pins is connected respectively to corresponding one of the column connections. The scanning scheme is employed to identify the row and column of the key having its key switch depressed. A keyswitch matrix having a total of (M-2)+(N-2) integrated circuit device pins can have a maximum of (M.times.N)-4 keys in the keypad.

摘要翻译： 公开了利用集成电路器件的电源引脚VDD和接地引脚GND的键盘结构的扫描方法。 集成电路器件具有多个行引脚和列引脚，电源引脚和接地引脚以及用于集成电路器件的其它功能的多个引脚。 集成电路设备的行和列引脚，电源引脚和接地引脚连接到具有多个行连接和列连接的键开关矩阵的相应连接。 扫描装置的键开关矩阵具有连接到电源引脚的行连接中的第一个。 扫描装置的键开关矩阵具有连接到接地引脚的行连接中的第二个。 每个其他行引脚分别连接到相应的行连接。 每个列引脚分别连接到对应的一个列连接。 使用扫描方案来识别其键开关被按压的键的行和列。 具有总共（M-2）+（N-2）个集成电路器件引脚的钥匙开关矩阵在键盘中可以具有最大的（M×N）-4个键。