公开(公告)号：US08724657B2

公开(公告)日：2014-05-13

申请号：US13205420

申请日：2011-08-08

申请人： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

发明人： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC分类号： H04J3/24 ,  H04L12/56

CPC分类号： H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

摘要： A method and system of packet assembly is provided. The method includes providing a first packet descriptor. The first packet descriptor is a pointer-to-pointer (P2P) descriptor that includes pointer information. The method further includes retrieving a first pointer referenced by the pointer information of the first packet descriptor; providing the first pointer to a DMA engine; and using the DMA engine to retrieve packet data referenced by the first pointer.

摘要翻译： 提供了一种分组组装的方法和系统。 该方法包括提供第一分组描述符。 第一个分组描述符是包括指针信息的指针指针（P2P）描述符。 该方法还包括：检索由第一分组描述符的指针信息引用的第一指针; 提供第一个指向DMA引擎的指针; 并使用DMA引擎来检索由第一个指针引用的数据包数据。

公开(公告)号：US20120008631A1

公开(公告)日：2012-01-12

申请号：US13154413

申请日：2011-06-06

申请人： David T. Hass

发明人： David T. Hass

IPC分类号： H04L12/56 ,  G06F12/08 ,  G06F9/30

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/30

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07995596B2

公开(公告)日：2011-08-09

申请号：US12120082

申请日：2008-05-13

申请人： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

发明人： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

摘要： A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.

摘要翻译： 提供了一种从软件中卸载数据包协议封装的方法。 在操作中，接收指针信息。 此外，使用指针信息，通过在硬件中组装分组，从软件卸载分组协议封装。

公开(公告)号：US07961723B2

公开(公告)日：2011-06-14

申请号：US10930456

申请日：2004-08-31

申请人： David T. Hass

发明人： David T. Hass

IPC分类号： H04L12/28

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/30

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07924828B2

公开(公告)日：2011-04-12

申请号：US10930455

申请日：2004-08-31

申请人： David T. Hass ,  Abbas Rashid

发明人： David T. Hass ,  Abbas Rashid

IPC分类号： H04L12/56

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/90

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20100042785A1

公开(公告)日：2010-02-18

申请号：US12582622

申请日：2009-10-20

申请人： David T. Hass ,  Abbas Rashid

发明人： David T. Hass ,  Abbas Rashid

IPC分类号： G06F15/76 ,  G06F12/08 ,  G06F9/02

CPC分类号： H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07627721B2

公开(公告)日：2009-12-01

申请号：US10897577

申请日：2004-07-23

申请人： David T. Hass

发明人： David T. Hass

IPC分类号： G06F12/00 ,  G06F15/16

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/30

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07509476B2

公开(公告)日：2009-03-24

申请号：US11704709

申请日：2007-02-08

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.

摘要翻译： 提出了用于在不同操作系统上执行软件应用的高级处理器，包括：多个处理器核，每个被配置为执行多个线程，其中每个处理器核心包括数据高速缓存和指令高速缓存; 数据交换互连环布置，与所述多个处理器核心中的每一个的数据高速缓存直接耦合，并且被配置为在所述多个处理器核之间传递存储器相关信息; 直接与多个处理器核心中的每一个的指令高速缓存和多个通信端口耦合的消息传递网络; 以及与所述多个处理器核心中的每一个耦合的存储器管理单元（MMU），所述MMU具有第一翻译后视缓冲器（TLB）部分，第二TLB部分和第三TLB部分，其中每个TLB部分可操作 几种模式，其中每个TLB部分包括多个条目。

公开(公告)号：US07461213B2

公开(公告)日：2008-12-02

申请号：US10897576

申请日：2004-07-23

申请人： David T. Hass ,  Rohini Krishna Kaza

发明人： David T. Hass ,  Rohini Krishna Kaza

IPC分类号： G06F12/00 ,  G06F15/16

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/15

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20080126709A1

公开(公告)日：2008-05-29

申请号：US11961884

申请日：2007-12-20

申请人： David T. Hass ,  Abbas Rashid

发明人： David T. Hass ,  Abbas Rashid

IPC分类号： G06F12/08

CPC分类号： H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。