公开(公告)号：US20080216074A1

公开(公告)日：2008-09-04

申请号：US11961910

申请日：2007-12-20

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F9/54 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个多线程处理器核心，每个处理器核心具有数据高速缓存和指令高速缓存。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20080140956A1

公开(公告)日：2008-06-12

申请号：US12018144

申请日：2008-01-22

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

公开(公告)号：US20120030445A1

公开(公告)日：2012-02-02

申请号：US13195785

申请日：2011-08-01

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07509476B2

公开(公告)日：2009-03-24

申请号：US11704709

申请日：2007-02-08

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.

摘要翻译： 提出了用于在不同操作系统上执行软件应用的高级处理器，包括：多个处理器核，每个被配置为执行多个线程，其中每个处理器核心包括数据高速缓存和指令高速缓存; 数据交换互连环布置，与所述多个处理器核心中的每一个的数据高速缓存直接耦合，并且被配置为在所述多个处理器核之间传递存储器相关信息; 直接与多个处理器核心中的每一个的指令高速缓存和多个通信端口耦合的消息传递网络; 以及与所述多个处理器核心中的每一个耦合的存储器管理单元（MMU），所述MMU具有第一翻译后视缓冲器（TLB）部分，第二TLB部分和第三TLB部分，其中每个TLB部分可操作 几种模式，其中每个TLB部分包括多个条目。

公开(公告)号：US07346757B2

公开(公告)日：2008-03-18

申请号：US10898150

申请日：2004-07-23

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/00

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US09092360B2

公开(公告)日：2015-07-28

申请号：US13195785

申请日：2011-08-01

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/10 ,  H04L12/931 ,  G06F12/08

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07991977B2

公开(公告)日：2011-08-02

申请号：US11961910

申请日：2007-12-20

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/00 ,  G06F15/173

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US09264380B2

公开(公告)日：2016-02-16

申请号：US13103041

申请日：2011-05-07

申请人： David T. Hass

发明人： David T. Hass

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  H04L12/931 ,  G06F12/08

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/30

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08949522B1

公开(公告)日：2015-02-03

申请号：US13165736

申请日：2011-06-21

申请人： Gaurav Garg ,  David T. Hass

发明人： Gaurav Garg ,  David T. Hass

IPC分类号： G06F13/00

CPC分类号： G06F13/385

摘要： Systems, apparatusses, and methods are disclosed for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU). The present disclosure teaches a processor system that employs out-of-order stride prefetch units. The out-of-order stride prefetch units are utilized for issuing prefetches for out-of-order stride access patterns. In one or more embodiments, the out-of-order stride prefetch units examine the offsets between past virtual address (VA) accesses and the directions of the past VA accesses in order to generate an estimate of the underlying VA access stride of the executed program code (PC). In at least one embodiment, the out-of-order stride prefetch units use the estimate of the VA access stride in order to generate a prediction of future VA accesses. In some embodiments, after the out-of-order stride prefetch units have generated the prediction of future VA accesses, the out-of-order stride prefetch units prefetch the predicted future VA accesses.

摘要翻译： 公开了用于改善无序中央处理单元（CPU）上的基于步长的预取器的性能的系统，装置和方法。 本公开教导了采用无序步长预取单元的处理器系统。 无序步幅预取单元用于发出无序步进访问模式的预取。 在一个或多个实施例中，无序步长预取单元检查过去虚拟地址（VA）访问与过去VA访问的方向之间的偏移量，以便生成执行程序的基本VA访问步幅的估计 代码（PC）。 在至少一个实施例中，无序步长预取单元使用VA访问步幅的估计，以便生成将来VA访问的预测。 在一些实施例中，在无序步幅预取单元已经产生未来VA访问的预测之后，无序步幅预取单元预取预测的未来VA访问。

公开(公告)号：US08671220B1

公开(公告)日：2014-03-11

申请号：US12325050

申请日：2008-11-28

申请人： Gaurav Garg ,  David T. Hass ,  Kaushik Kuila ,  Gaurav Singh

发明人： Gaurav Garg ,  David T. Hass ,  Kaushik Kuila ,  Gaurav Singh

IPC分类号： G06F15/167 ,  G06F15/173

CPC分类号： H04L47/10 ,  H04L49/103 ,  H04L49/109

摘要： A network-on-chip system, method, and computer program product are provided for transmitting messages utilizing a centralized on-chip shared memory switch. In operation, a message is sent from one of a plurality of agents connected on a messaging network. The message is received at a central shared memory switch, the central shared memory switch being in communication with each of the plurality of agents. Further, the message is transmitted from the central shared memory switch to a destination agent, the destination agent being one of the plurality of agents.

摘要翻译： 提供了片上系统，方法和计算机程序产品，用于使用集中的片上共享存储器交换机来发送消息。 在操作中，从连接在消息收发网络上的多个代理之一发送消息。 消息在中央共享存储交换机处被接收，中央共享存储器交换机与多个代理中的每一个进行通信。 此外，消息从中央共享存储交换机发送到目的地代理，目的地代理是多个代理之一。