公开(公告)号：US20220156556A1

公开(公告)日：2022-05-19

申请号：US17446685

申请日：2021-09-01

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kwang IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Jae-Jin LEE

IPC: G06N3/04 ,  G06N3/063 ,  H03K19/20

Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a first synapse zone and a second synapse zone each including one or more synapses, wherein each of the synapses is configured to perform an operation based on the input spike signal and each weight, and a neuron circuit that generates an output spike signal based on operation results of the synapses. The input spike signal is transferred to the first synapse zone and the second synapse zone through a tree structure, and each of branch nodes of the tree structure includes a driving buffer.

公开(公告)号：US20210295511A1

公开(公告)日：2021-09-23

申请号：US17339574

申请日：2021-06-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kwang IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Mi Jeong PARK ,  Seong Mo PARK ,  Hyung-IL PARK ,  Jae-Jin LEE ,  In Gi LIM

IPC: G06T7/00 ,  A61B1/00 ,  A61B1/04 ,  A61B5/00 ,  G16H30/20 ,  G06N3/08 ,  G16H50/70 ,  G16H30/40 ,  G06N3/04

Abstract: Provided is a capsule endoscope. The capsule endoscope includes: an imaging device configured to perform imaging on a digestive tract in vivo to generate an image; an artificial neural network configured to determine whether there is a lesion area in the image; and a transmitter configured to transmit the image based on a determination result of the artificial neural network.

公开(公告)号：US20200160146A1

公开(公告)日：2020-05-21

申请号：US16688746

申请日：2019-11-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kwang IL OH ,  Sung Eun KIM ,  Seong Mo PARK ,  Young Hwan BAE ,  Jae-Jin LEE ,  In Gi LIM

IPC: G06N3/04 ,  H03K5/24 ,  G06N3/08 ,  G06N3/063

Abstract: Provided is a spike neural network circuit including a synapse configured to generate an operation signal based on an input spike signal and a weight, and a neuron configured to generate an output spike signal using a comparator configured to compare a voltage of a membrane signal generated based on the operation signal with a voltage of a threshold signal, wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator depending on the membrane signal.

公开(公告)号：US20200067516A1

公开(公告)日：2020-02-27

申请号：US16542469

申请日：2019-08-16

Applicant: Electronics and Telecommunications Research Institute

Inventor： KWANG IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Mi Jeong PARK ,  Hyung-IL PARK ,  Kyung Jin BYUN ,  Jae-Jin LEE ,  In Gi LIM

IPC: H03L7/093

Abstract: The inventive concept includes an oscillating circuit, a phase inverting circuit, and a phase detecting circuit. The oscillating circuit generates a first clock to be used to sample an input signal. The phase inverting circuit outputs a second clock based on the first clock. The phase detecting circuit generates a control signal having a first logic value when a phase difference between a phase of the input signal and a phase of the second clock is less than a reference value for a reference time or more. The phase detecting circuit generates the control signal having a second logic value when the phase difference is equal to or greater than the reference value or when the phase difference is less than the reference value for a time shorter than the reference time. The phase inverting circuit inverts the phase of the second clock when a logic value of the control signal changes from the first logic value to the second logic value or when a logic value of the control signal changes from the second logic value to the first logic value.

公开(公告)号：US20190245532A1

公开(公告)日：2019-08-08

申请号：US16262738

申请日：2019-01-30

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Tae Wook KANG ,  Jae-Jin LEE ,  Kwang IL OH ,  Sung Eun KIM ,  Sukho LEE ,  Kyuseung HAN

IPC: H03K17/14 ,  H03K17/08

CPC classification number: H03K17/145 ,  H03K17/08 ,  H03K2017/0806 ,  H03K2217/0027

Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.

公开(公告)号：US20180232635A1

公开(公告)日：2018-08-16

申请号：US15804912

申请日：2017-11-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kwang IL OH ,  Sung Eun KIM ,  Seong Mo PARK ,  Hyung-IL PARK ,  Jae-Jin LEE ,  Joo Hyun LEE

IPC: G06N3/063 ,  G06F7/68 ,  G06F5/01

CPC classification number: G06N3/0635 ,  G06F5/01 ,  G06F7/68 ,  H03K19/20

Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

公开(公告)号：US20160110209A1

公开(公告)日：2016-04-21

申请号：US14793259

申请日：2015-07-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Jin LEE

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/455 ,  G06F9/5011

Abstract: The present invention relates to multi-core emulation, more specifically to a method and an apparatus for high-speed multi-core emulation using a multi-threading functionality of a computer.An apparatus for multi-core emulation based on multi-threading in accordance with the present invention includes: an emulation manager configured to emulate a plurality of cores simultaneously by generating emulation function for the plurality of cores, respectively, as respective threads; and a resource scheduler configured to adjust an order of use of shared resources so as not to have a race condition occurred between two or more cores of the plurality of cores accessing the shared resources simultaneously.

Abstract translation: 本发明涉及多核仿真，更具体地涉及使用计算机的多线程功能的用于高速多核仿真的方法和装置。 一种用于根据本发明的基于多线程的多核仿真的装置，包括：仿真管理器，被配置为分别通过针对多个核分别产生作为相应线程的仿真功能来同时仿真多个核心; 以及资源调度器，被配置为调整共享资源的使用顺序，以便在同时访问共享资源的多个核心的两个或更多个核之间发生竞争条件。

公开(公告)号：US20140359225A1

公开(公告)日：2014-12-04

申请号：US14287344

申请日：2014-05-27

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae-Jin LEE

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0848 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/6042

Abstract: Disclosed herein is a multi-core processor including: a plurality of processor cores; a shared data cache storing cache data previously accessed by at least one of the plurality of processor cores; and an address decoder comparing an address value of a data required by at least one of the plurality of processor cores and a set address register value with each other and allowing at least one of the plurality of processor cores to access the shared data cache or a separate memory in which non-cacheable data that are not stored in the shared data cache are stored.

Abstract translation: 本文公开了一种多核处理器，包括：多个处理器核; 存储先前由所述多个处理器核心中的至少一个访问的高速缓存数据的共享数据高速缓存; 以及地址解码器，将多个处理器核心中的至少一个处理器核心所需的数据的地址值和设置的地址寄存器值彼此进行比较，并允许多个处理器核心中的至少一个访问共享数据高速缓存或 存储不存储在共享数据高速缓存中的非可缓存数据的单独存储器。