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公开(公告)号：US20120210070A1
公开(公告)日：2012-08-16
申请号：US13450871
申请日：2012-04-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0895
摘要： A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory.
摘要翻译： 提供了一种数据缓冲机制。 高速缓存的一部分被分配为缓冲区，高速缓存的另一部分被指定为随机存取存储器（RAM）。 一个缓冲区被分配给一个处理器。 根据处理器的指令将数据块存储到高速缓冲存储器的一个缓冲区。 数据块从缓存的缓冲区中的一个存储到存储器。
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52.发明申请公开(公告)号：US20110320892A1
公开(公告)日：2011-12-29
申请号：US12821271
申请日：2010-06-23
CPC分类号： G06F11/0745 , G06F11/0724 , G06F11/0793 , G06F12/1458
摘要： A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.
摘要翻译： 提供了一种用于隔离计算机系统中的错误的系统和计算机实现的方法。 该方法包括接收访问计算机存储器的直接存储器访问（DMA）命令，读取响应或中断; 将DMA命令与由流标识（ID）标识的流相关联以访问计算机存储器，读取响应或中断; 检测由流中的DMA命令引起的存储器错误，存储器错误导致计算机存储器中的过时数据; 并且在检测到存储器错误时，将与流ID相关联的流中的存储器错误与其他流ID相关联的其他流隔离。
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公开(公告)号：US20110320730A1
公开(公告)日：2011-12-29
申请号：US12821963
申请日：2010-06-23
CPC分类号： G06F12/0895
摘要： A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory.
摘要翻译： 提供了一种数据缓冲机制。 高速缓存的一部分被分配为缓冲区，高速缓存的另一部分被指定为随机存取存储器（RAM）。 一个缓冲区被分配给一个处理器。 根据处理器的指令将数据块存储到高速缓冲存储器的一个缓冲区。 数据块从缓存的缓冲区中的一个存储到存储器。
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54.发明授权Processor memory array having memory macros for relocatable store protect keys 失效处理器存储器阵列具有用于可重定位存储保护键的存储器宏公开(公告)号：US07590899B2
公开(公告)日：2009-09-15
申请号：US11532267
申请日：2006-09-15
申请人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford, III , Kevin W. Kark , Pak-kin Mak , Liyong Wang
发明人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford, III , Kevin W. Kark , Pak-kin Mak , Liyong Wang
CPC分类号： G06F12/1416
摘要： A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.
摘要翻译： 用于主机主存储子系统的DDR SDRAM DIMM具有在具有第一侧和第二侧的矩形印刷电路板上的多个DDR SDRAM，长度（152MM = 6英寸）在149和153毫米之间，并且在149.15mm处优化 或151.35mm的长度，第一和第二端的宽度小于长度; 所述第一侧的第一多个连接器位置沿所述板的第一边缘延伸，所述第一边延伸所述板的长度，所述第二侧的第二多个连接器位置在所述板的第一边缘上延伸，定位键具有其 中心位于第一个边缘，位于80 mm和86 mm之间，并使用1.5 mm宽的定位键进行优化，定位键距离板的第一端81.58或85.67 mm，位于64至70 mm之间，并以定位键为中心进行优化 从板的第二端67.58或65.675。 每个DIMM具有包括以下称为存储宏的多个物理实体中的一个的存储器区域，其是在DIMM物理存储器中包含SP密钥和数据集存储的可重定位区域。 这些内存宏SP键区域为主存储器定义了一个具有硬物理边界的任意逻辑结构。
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55.发明授权Method for ensuring fairness among requests within a multi-node computer system 有权确保多节点计算机系统内的请求之间的公平性的方法公开(公告)号：US07523267B2
公开(公告)日：2009-04-21
申请号：US11532156
申请日：2006-09-15
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译： 使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止 成功了 通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否 资源有效，但在请求完成之前遇到一些需要解决的冲突。 只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成 请求被允许进入系统。
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56.发明授权Method for ensuring system serialization (quiesce) in a multi-processor environment 有权确保多处理器环境中系统序列化（quiesce）的方法公开(公告)号：US07379418B2
公开(公告)日：2008-05-27
申请号：US10436320
申请日：2003-05-12
申请人： Steven A. Korb , Pak-kin Mak
发明人： Steven A. Korb , Pak-kin Mak
CPC分类号： H04L12/2854
摘要： A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are made known and predictable greatly simplify the task of coordinating quiesce responses within the system. When latencies are not fixed and topologies such as open or closed bus architectures are be used a more dynamic approach is required to ensure system serialization. Adaptive quiesce logic on each node's SCE can dynamically identify the role of the node within the system and automatically configure itself to guarantee that no enabled processor within the entire system receives a quiesce indication before all processors have reached the stopped state. This is also true for systems where nodes are being concurrently added or removed during system operation. Bus states process quiesce requests. Also this method of reaching a quiesced state operates independently of differing latencies between nodes. Defined master slave end and interior nodes are used within the quiesce network.
摘要翻译： 在多处理器多节点环境中确保系统序列化的方法被用于强制多处理器环境中的所有处理器在一个处理器改变系统状态时临时挂起操作。 节点之间的延迟已知和可预测的架构设计大大简化了系统内协调静默响应的任务。 当延迟不固定并且使用诸如开放或封闭总线架构的拓扑结构时，需要采用更加动态的方法来确保系统序列化。 每个节点的SCE上的自适应静默逻辑可以动态地识别系统中节点的角色，并自动配置自身，以确保在所有处理器都已经达到停止状态之前，整个系统内没有启用的处理器收到静默指示。 在系统运行期间同时添加或删除节点的系统也是如此。 总线状态处理停顿请求。 此外，达到静止状态的这种方法独立于节点之间的不同延迟。 定义的主从端和内部节点在静默网络内使用。
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57.发明申请Processor memory array having memory macros for relocatable store protect keys 失效处理器存储器阵列具有用于可重定位存储保护键的存储器宏公开(公告)号：US20080072109A1
公开(公告)日：2008-03-20
申请号：US11532267
申请日：2006-09-15
申请人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford , Kevin W. Kark , Pak-kin Mak , Liyong Wang
发明人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford , Kevin W. Kark , Pak-kin Mak , Liyong Wang
CPC分类号： G06F12/1416
摘要： A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.
摘要翻译： 用于主机主存储子系统的DDR SDRAM DIMM具有在具有第一侧和第二侧的矩形印刷电路板上的多个DDR SDRAM，长度（152MM = 6英寸）在149和153毫米之间，并且在149.15mm处优化 或151.35mm的长度，第一和第二端的宽度小于长度; 所述第一侧的第一多个连接器位置沿所述板的第一边缘延伸，所述第一边延伸所述板的长度，所述第二侧的第二多个连接器位置在所述板的第一边缘上延伸，定位键具有其 中心位于第一个边缘，位于80 mm和86 mm之间，并使用1.5 mm宽的定位键进行优化，定位键距离板的第一端81.58或85.67 mm，位于64至70 mm之间，并以定位键为中心进行优化 从板的第二端67.58或65.675。 每个DIMM具有包括以下称为存储宏的多个物理实体中的一个的存储器区域，其是在DIMM物理存储器中包含SP密钥和数据集存储的可重定位区域。 这些内存宏SP键区域为主存储器定义了一个具有硬物理边界的任意逻辑结构。
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公开(公告)号：US20080071964A1
公开(公告)日：2008-03-20
申请号：US11532294
申请日：2006-09-15
申请人： Kevin W. Kark , Liyong Wang , Carl B. Ford , Pak-kin Mak
发明人： Kevin W. Kark , Liyong Wang , Carl B. Ford , Pak-kin Mak
IPC分类号： G06F12/14
CPC分类号： G06F12/1475 , G06F11/08
摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-etect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.
摘要翻译： 存储保护密钥和系统数据共享相同的物理存储。 关键区域是通过固件动态重新定位。 配置阵列用于将关键区域的绝对地址映射到其物理地址。 即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。 使用三重等效双重ECC方案来保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。 额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。 在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。 我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。
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公开(公告)号：US07111130B2
公开(公告)日：2006-09-19
申请号：US11402599
申请日：2006-04-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0831
摘要： A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.
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公开(公告)号：US06654925B1
公开(公告)日：2003-11-25
申请号：US09650153
申请日：2000-08-29
申请人： Patrick J. Meaney , Pak-kin Mak
发明人： Patrick J. Meaney , Pak-kin Mak
IPC分类号： G11C2900
CPC分类号： G06F12/0855
摘要： Disclosed is an apparatus and means for searching a cache directory with full ECC support without the latency of the ECC logic on every directory search. The apparatus allows for bypassing the ECC logic in an attempt to search the directory. When a correctable error occurs which causes the search results to differ, a retry will occur with the corrected results used on the subsequent pass. This allows for the RAS characteristics of full ECC but the delay of the ECC path will only be experienced when a correctable error occurs, thus reducing average latency of the directory pipeline significantly. Disclosed is also a means for notifying the requester of a retry event and the ability to retry the search in the event that the directory is allowed to change between passes.
摘要翻译： 公开了一种用于在没有ECC逻辑在每个目录搜索上的等待时间的情况下用完整的ECC支持来搜索高速缓存目录的装置和装置。 该设备允许绕过ECC逻辑以尝试搜索目录。 当出现可导致搜索结果不同的可纠正错误时，会在随后的通过中使用更正的结果进行重试。 这允许完整ECC的RAS特性，但是仅当出现可纠正错误时才会经历ECC路径的延迟，从而显着减少目录管道的平均延迟。 还公开了一种用于通知请求者重试事件的手段，以及在目录被允许在遍之间改变的情况下重试搜索的能力。
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