公开(公告)号：US11870780B2

公开(公告)日：2024-01-09

申请号：US18181432

申请日：2023-03-09

Applicant: Google LLC

Inventor： Benjamin C. Serebrin

IPC: H04L9/40 ,  G06F12/14 ,  G06F21/79 ,  G06F12/1081 ,  H04L9/32

CPC classification number: H04L63/0876 ,  G06F12/1081 ,  G06F12/1408 ,  G06F12/1475 ,  G06F21/79 ,  H04L9/3247 ,  H04L63/062 ,  H04L63/164 ,  G06F2212/1052

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.

公开(公告)号：US11868274B2

公开(公告)日：2024-01-09

申请号：US17341988

申请日：2021-06-08

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/00 ,  G06F12/14 ,  G06F12/1018 ,  G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G06F21/71

CPC classification number: G06F12/1408 ,  G06F12/1018 ,  G06F12/1475 ,  G06F21/602 ,  G06F21/71 ,  G06F21/79 ,  H04L9/0861 ,  H04L9/0894 ,  G06F2212/1052

Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a secure zone configured to store keys and an unscrambled zone configured to operate on unscrambled data. The processor can convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data. Another processor may also be coupled with the memory, but can be prevented from accessing the unscrambled data in the unscrambled zone.

公开(公告)号：US11829299B2

公开(公告)日：2023-11-28

申请号：US17819418

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Men Long

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/14 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/1081

CPC classification number: G06F12/1027 ,  G06F9/3005 ,  G06F12/1408 ,  G06F12/1475 ,  G06F12/1045 ,  G06F12/1081 ,  G06F2212/402 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/652 ,  G06F2212/657 ,  Y02D10/00

Abstract: Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

公开(公告)号：US20230216848A1

公开(公告)日：2023-07-06

申请号：US18181432

申请日：2023-03-09

Applicant: Google LLC

Inventor： Benjamin C. Serebrin

IPC: H04L9/40 ,  G06F12/14 ,  G06F21/79 ,  G06F12/1081 ,  H04L9/32

CPC classification number: H04L63/0876 ,  G06F12/1475 ,  G06F21/79 ,  G06F12/1081 ,  G06F12/1408 ,  H04L9/3247 ,  H04L63/062 ,  H04L63/164 ,  G06F2212/1052

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.

公开(公告)号：US20180247069A1

公开(公告)日：2018-08-30

申请号：US15753270

申请日：2016-08-04

Applicant: The Trustees of Columbia University in the City of New Yoirk

Inventor： Adrian Tang ,  Salvatore Stolfo ,  Lakshminarasimhan Sethumadhavan

IPC: G06F21/62 ,  G06F21/52 ,  G06F21/60 ,  G06F12/14 ,  G06F12/1009 ,  G06F9/455

CPC classification number: G06F21/6218 ,  G06F9/45558 ,  G06F12/1009 ,  G06F12/1475 ,  G06F21/52 ,  G06F21/604 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes determining whether an operation to access a memory location containing executable code comprises a general-purpose memory access operation, and changing content of the memory location in response to a determination that the operation to access the memory location containing the executable code comprises the general-purpose memory access operation to the memory location.

公开(公告)号：US09959309B2

公开(公告)日：2018-05-01

申请号：US14532850

申请日：2014-11-04

Applicant: Tenoware R&D Limited

Inventor： Pavan K. Mettu ,  Avinash Kumar

IPC: G06F17/00 ,  G06F17/30 ,  G06F9/52 ,  G06F12/14 ,  G06F3/06

CPC classification number: G06F17/30362 ,  G06F3/062 ,  G06F3/0637 ,  G06F3/067 ,  G06F9/526 ,  G06F12/1475

Abstract: Example distributed reservation systems and methods are described. In one implementation, multiple storage nodes are configured to store distributed data. Multiple clients are coupled to the multiple storage nodes and access data from the multiple storage nodes. A management server is coupled to the multiple storage nodes and the multiple clients. The management server manages the access of data by the multiple clients and manages reservation of the multiple storage nodes by a particular client.

公开(公告)号：US20180024944A1

公开(公告)日：2018-01-25

申请号：US15217728

申请日：2016-07-22

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Mitchel Humpherys

IPC: G06F12/14 ,  G06F12/1009

CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F12/1416 ,  G06F12/145 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/152

Abstract: Disclosed are methods and apparatus for memory management in shared virtual memory (SVM) systems. The methods and apparatus provide SVM access control on a per master basis through the assignment of a first classification identifier (ID) upon reception of a memory access request from a memory master. The assigned first classification ID assigned to the memory request is compared with a second classification ID stored in at least one page table entry of a page table used to manage the SVM system. The page table entry (PTE) corresponds to one or more memory locations of the SVM being requested in the memory access request. SVM system access operations for the memory access request are then denied if the first classification ID does not match the second classification ID, thereby providing added per master access control for the SVM system.

公开(公告)号：US20180018260A1

公开(公告)日：2018-01-18

申请号：US15627931

申请日：2017-06-20

Applicant: FUJITSU TEN LIMITED

Inventor： Masaru SUGIHARA

IPC: G06F12/06

CPC classification number: G06F12/0653 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/1475 ,  G06F2212/1052

Abstract: An information processing device according to an embodiment includes a memory and a mediation unit. The memory includes memory use areas that are allocated to respective tasks, and an identification-information area that identifies the tasks. The mediation unit mediates writing and reading, by one of the tasks, into and from one of the memory use areas. When accepting a request of the writing and reading from the one task, the mediation unit writes one of the identification informations corresponding to the one task into the identification-information area, further reads information memorized in the identification-information area at a predetermined timing, and detects an abnormality in the memory on the basis of the read information.

公开(公告)号：US09858199B1

公开(公告)日：2018-01-02

申请号：US15085660

申请日：2016-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Andrea Olgiati

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F12/1475 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A system and method for allocating shared inter-process memory by a memory management unit is disclosed. A memory management unit may receive information indicative of allocating a region of shared memory. The information may further indicate that a second process may share access to the memory. The memory management unit may identify corresponding regions of virtual address space for each process, such that the region in each address space maps to the same range of addresses. The memory management unit may virtualize access to the shared memory by mapping from the corresponding regions of the virtual address space.

公开(公告)号：US20170364455A1

公开(公告)日：2017-12-21

申请号：US15691874

申请日：2017-08-31

Applicant: LZLABS GMBH

Inventor： Jan Jaeger

IPC: G06F12/14 ,  G06F21/79 ,  G06F21/00

CPC classification number: G06F12/1475 ,  G06F12/145 ,  G06F12/1466 ,  G06F21/00 ,  G06F21/79 ,  G06F2212/1052

Abstract: A system is described to provide protection key access control in a system whose operating system and processor were not designed to provide a protection key memory access control mechanism. Such a system can be applied to an emulator or to enable a system that executes native applications to be interoperable with a legacy system that employs protection key memory access control.