公开(公告)号：US20130126983A1

公开(公告)日：2013-05-23

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US08304835B2

公开(公告)日：2012-11-06

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/36

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（IGFET）不同地使用的空阱区域和填充阱区域的组合，以实现期望的电子 特点 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US08304308B2

公开(公告)日：2012-11-06

申请号：US13198601

申请日：2011-08-04

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea

IPC: H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (275-1 and 277-1) laterally conform to opposite first and second lower edges (297-1 and 299-1) of the base link portion so as to determine, and thereby control, its length.

Abstract translation: 半导体结构包含双极晶体管（101）和间隔结构（265-1或265-2）。 晶体管具有发射极（241），基极（243）和集电极（245）。 基部形成有本征基部（243I），基部连接部（243L）和基部接触部（245C）。 本征基部位于发射极之下和集电极材料之上。 基部连接部在本征基部与基部接触部之间延伸。 间隔结构包括隔离电介质层（267-1或267-2）和间隔部件。 电介质层沿着上半导体表面延伸。 间隔部件包括位于基部连接部分上方的电介质层上的大部分非单晶半导体材料（优选多晶半导体材料）的侧向间隔部分（269-1或269-2）。 横向间隔部分（275-1和277-1）的相对的第一和第二上边缘横向地与基部连杆部分的相对的第一和第二下边缘（297-1和299-1）相一致，以便确定，从而 控制，其长度。

公开(公告)号：US20120181626A1

公开(公告)日：2012-07-19

申请号：US13298284

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）具有用于实现高性能的空井区域。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地基本上单调减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US20100244143A1

公开(公告)日：2010-09-30

申请号：US12382966

申请日：2009-03-27

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea

IPC: H01L27/06 ,  H01L27/082 ,  H01L21/8228 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (275-1 and 277-1) laterally conform to opposite first and second lower edges (297-1 and 299-1) of the base link portion so as to determine, and thereby control, its length.

Abstract translation: 半导体结构包含双极晶体管（101）和间隔结构（265-1或265-2）。 晶体管具有发射极（241），基极（243）和集电极（245）。 基部形成有本征基部（243I），基部连接部（243L）和基部接触部（245C）。 本征基部位于发射极之下和集电极材料之上。 基部连接部在本征基部与基部接触部之间延伸。 间隔结构包括隔离电介质层（267-1或267-2）和间隔部件。 电介质层沿着上半导体表面延伸。 间隔部件包括位于基部连接部分上方的电介质层上的大部分非单晶半导体材料（优选多晶半导体材料）的侧向间隔部分（269-1或269-2）。 横向间隔部分（275-1和277-1）的相对的第一和第二上边缘横向地与基部连杆部分的相对的第一和第二下边缘（297-1和299-1）相一致，以便确定，从而 控制，其长度。

公开(公告)号：US20100244128A1

公开(公告)日：2010-09-30

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（“IGFET”）不同地使用的空阱区域和填充阱区域的组合，以实现 所需的电子特性。 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US07642574B2

公开(公告)日：2010-01-05

申请号：US11981481

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US20080308878A1

公开(公告)日：2008-12-18

申请号：US11981481

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US07235862B2

公开(公告)日：2007-06-26

申请号：US09903059

申请日：2001-07-10

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/7391 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

Abstract translation: 半导体结变容二极管利用栅极增强来使变容二极管实现最大电容与最小电容的高比率。

公开(公告)号：US07067879B1

公开(公告)日：2006-06-27

申请号：US10857152

申请日：2004-05-28

Applicant: Terry Dyer ,  Jim McGinty ,  Andrew Strachan ,  Constantin Bulucea

Inventor： Terry Dyer ,  Jim McGinty ,  Andrew Strachan ,  Constantin Bulucea

IPC: H01L29/72

CPC classification number: H01L29/7813 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in that only two extra mask steps are added to the existing BCD process, instead of the 10 or so mask steps used in existing discrete trench DMOS processes. Further, the location of these additional heat cycles in the BCD process steps can be placed so as to have minimal impact on the other components created in the process. Utilizing an integrated trench device in a BCD process can offer at least a factor-of-two RDS(ON) area advantage over a planar counterpart.

Abstract translation: 垂直沟槽DMOS器件的形成可以添加到现有的集成BCD工艺流程中，以提高BCD器件的效率。 这种沟槽DMOS的形成与使用离散沟槽DMOS器件的现有方法不同，因为在现有的BCD工艺中仅添加了两个额外的掩模步骤，而不是现有离散沟槽DMOS工艺中使用的10个掩模步骤。 此外，BCD工艺步骤中这些额外的热循环的位置可以被放置成对在该过程中产生的其它部件的影响最小。 利用BCD处理中的集成沟槽器件可以提供比平面对等物至少两个因子二的DS（ON）区域优点。