公开(公告)号：US08304835B2

公开(公告)日：2012-11-06

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/36

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（IGFET）不同地使用的空阱区域和填充阱区域的组合，以实现期望的电子 特点 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US20100244128A1

公开(公告)日：2010-09-30

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（“IGFET”）不同地使用的空阱区域和填充阱区域的组合，以实现 所需的电子特性。 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US5844299A

公开(公告)日：1998-12-01

申请号：US791987

申请日：1997-01-31

Applicant: Richard Billings Merrill ,  Donald M. Archer

Inventor： Richard Billings Merrill ,  Donald M. Archer

IPC: H01L21/02 ,  H01L29/00

CPC classification number: H01L28/10

Abstract: An integrated inductor with filled etch includes a substrate of semiconductor material which includes a surface and a cavity disposed therein, a mass of dielectric material disposed within the cavity, a layer of dielectric material disposed upon the mass of dielectric material, and a patterned layer of conductive material disposed upon the layer of dielectric material, such that the integrated inductor is formed without an oxide bridge. Thus, the integrated inductor has a rugged architecture.

Abstract translation: 具有填充蚀刻的集成电感器包括半导体材料的衬底，其包括设置在其中的表面和空腔，设置在空腔内的介电材料块，设置在电介质材料块上的介电材料层，以及设置在 导电材料设置在电介质材料层上，使得集成电感器形成为没有氧化物桥。 因此，集成电感器具有坚固的结构。

公开(公告)号：US5311115A

公开(公告)日：1994-05-10

申请号：US104827

申请日：1993-08-11

Applicant: Donald M. Archer

Inventor： Donald M. Archer

IPC: G05F3/26 ,  H01L27/088 ,  H03F3/343 ,  H03F3/345 ,  G05F3/16

CPC classification number: G05F3/262 ,  H01L27/0883

Abstract: An improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-channel transistor devices are provided as the cascode devices. A "diode connected" depletion device may be inserted between the enhancement gate and the drain of the current reference transistor to reduce saturation voltage. The "diode connected" depletion device keeps the drains of the enhancement devices at a similar voltage even when the enhancement and depletion device threshold, i.e. V.sub.T, do not track over temperature or process. Thus, the current mirror circuit provides not only higher output impedance, lower saturation voltage, but is also less sensitive to process variation.

Abstract translation: 通过使用增强型P沟道晶体管器件作为电流镜来实现具有高输出阻抗，低饱和电压和对工艺参数的较小灵敏度的改进的电流源，而耗尽P沟道晶体管器件被提供为共源共栅器件。 “二极管连接”耗尽装置可以插入在电流参考晶体管的增强栅极和漏极之间以降低饱和电压。 即使当增强和耗尽装置阈值（即VT）不跟踪温度或过程时，“二极管连接”耗尽装置仍将增强装置的排水管保持在相似的电压。 因此，电流镜电路不仅提供更高的输出阻抗，更低的饱和电压，而且对工艺变化也不太敏感。

公开(公告)号：US08377768B2

公开(公告)日：2013-02-19

申请号：US13293096

申请日：2011-11-09

Applicant: Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

Inventor： Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

IPC: H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract translation: 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。

公开(公告)号：US5808513A

公开(公告)日：1998-09-15

申请号：US988346

申请日：1997-12-10

Applicant: Donald M. Archer

Inventor： Donald M. Archer

IPC: H03F3/45

CPC classification number: H03F3/45479 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2203/45371 ,  H03F2203/45676

Abstract: A rail-to-rail input common mode range differential amplifier operates on rail-to-rail voltages down to approximately one volt by utilizing one p-channel transistor to cover a first portion of the common mode range, and a second p-channel transistor to cover a second portion of the common mode range.

Abstract translation: 轨到轨输入共模范围差分放大器通过利用一个p沟道晶体管覆盖共模范围的第一部分而工作在低至大约一伏的轨到轨电压，以及第二p沟道晶体管 以覆盖共模范围的第二部分。

公开(公告)号：US5764101A

公开(公告)日：1998-06-09

申请号：US855156

申请日：1997-05-13

Applicant: Donald M. Archer

Inventor： Donald M. Archer

IPC: H03F3/45

CPC classification number: H03F3/45479 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2203/45371 ,  H03F2203/45676

Abstract: A rail-to-rail input common mode range differential amplifier operates on rail-to-rail voltages down to approximately one volt by utilizing one p-channel transistor to cover a first portion of the common mode range, and a second p-channel transistor to cover a second portion of the common mode range.

公开(公告)号：US20100244131A1

公开(公告)日：2010-09-30

申请号：US12382969

申请日：2009-03-27

Applicant: Constantin Bulucea ,  William D. French ,  Sandeep R. Bahl ,  Jeng-Jiun Yang ,  D. Courtney Parker ,  Peter B. Johnson ,  Donald M. Archer

Inventor： Constantin Bulucea ,  William D. French ,  Sandeep R. Bahl ,  Jeng-Jiun Yang ,  D. Courtney Parker ,  Peter B. Johnson ,  Donald M. Archer

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/7835

Abstract: An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or 182) of a semiconductor body. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A more heavily doped pocket portion (250 or 290) of the body material extends largely along only the source. The source has a main source portion (240M or 280M) and a more lightly doped lateral source extension (240E or 280E). The drain has a main portion (242M or 282M) and a more lightly doped lateral drain extension (242E or 282E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Abstract translation: 不对称绝缘栅场效应晶体管（100或102）具有由主体材料（180或182）的沟道区（244或284）横向隔开的源（240或280）和漏极（242或282） 半导体体。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 主体材料的更加重掺杂的袋部分（250或290）主要仅沿着源头延伸。 源极具有主源部分（240M或280M）和更轻掺杂的侧向源延伸部（240E或280E）。 漏极具有主要部分（242M或282M）和更轻掺杂的侧向漏极延伸部（242E或282E）。 漏极延伸比源极延伸更轻的掺杂。 限定两个延伸的半导体掺杂剂的最大浓度在漏极延伸中比在源极延伸中更深。 另外或替代地，漏极延伸部在栅极电极之下进一步横向延伸，而不是源极延伸部分。 这些特性使得阈值电压在运行时间内稳定。

公开(公告)号：US20120264263A1

公开(公告)日：2012-10-18

申请号：US13293096

申请日：2011-11-09

Applicant: Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

Inventor： Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

IPC: H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract translation: 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。

公开(公告)号：US08101479B2

公开(公告)日：2012-01-24

申请号：US12382977

申请日：2009-03-27

Applicant: D. Courtney Parker ,  Donald M. Archer ,  Sandeep R. Bahl ,  Constantin Bulucea ,  William D. French ,  Peter B. Johnson ,  Jeng-Jiun Yang

Inventor： D. Courtney Parker ,  Donald M. Archer ,  Sandeep R. Bahl ,  Constantin Bulucea ,  William D. French ,  Peter B. Johnson ,  Jeng-Jiun Yang

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A gate electrode (302) of a field-effect transistor (102) is defined above, and vertically separated by a gate dielectric layer (300) from, a channel-zone portion (284) of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion (290) using the gate electrode as a dopant-blocking shield. A spacer (304T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (280M and 282M) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (304). Electrical contacts (310 and 312) are formed respectively to the source/drain portions.

Abstract translation: 场效应晶体管（102）的栅电极（302）定义在上面，并由半导体本体的主体材料的沟道区部分（284）由栅介质层（300）垂直分隔开。 半导体掺杂剂被引入主体材料中以限定使用栅电极作为掺杂剂阻挡屏蔽的更重掺杂的凹穴部分（290）。 具有沿着栅电极设置的电介质部分的隔离物（304T），设置在主体上的电介质部分和大部分占据其它两个间隔部分之间空间的填充部分（SC）。 半导体掺杂剂被引入体内以使用栅极电极和间隔物作为掺杂剂阻挡屏蔽来限定一对源/漏部分（280M和282M）。 去除填料垫片部分以将间隔件转换成L形（304）。 电触点（310和312）分别形成到源极/漏极部分。