公开(公告)号：US20240395722A1

公开(公告)日：2024-11-28

申请号：US18789993

申请日：2024-07-31

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US12142570B2

公开(公告)日：2024-11-12

申请号：US17975223

申请日：2022-10-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US11574877B2

公开(公告)日：2023-02-07

申请号：US17088606

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/16 ,  H01L21/48 ,  H01L23/498

Abstract: According to various examples, a device is described. The device may include a stiffener member including a first step section and a second step section. The device may also include a plurality of vias extending from or through the stiffener member. The device may be coupled to a printed circuit board.

公开(公告)号：US11476198B2

公开(公告)日：2022-10-18

申请号：US17024182

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kok Keng Wan

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/50 ,  H01L21/60

Abstract: Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.

公开(公告)号：US20220302033A1

公开(公告)日：2022-09-22

申请号：US17631254

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

Abstract: Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.

公开(公告)号：US20220278084A1

公开(公告)日：2022-09-01

申请号：US17638039

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L25/00

Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

公开(公告)号：US11342289B2

公开(公告)日：2022-05-24

申请号：US17087667

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim ,  Kooi Chi Ooi

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01G4/224 ,  H01L23/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

公开(公告)号：US11227841B2

公开(公告)日：2022-01-18

申请号：US16419683

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/00 ,  H01L23/522

Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.

公开(公告)号：US11205622B2

公开(公告)日：2021-12-21

申请号：US16423561

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/552 ,  H01L23/522

Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.

公开(公告)号：US20210183755A1

公开(公告)日：2021-06-17

申请号：US17023042

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/498 ,  H01L23/552 ,  H01L21/48

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.