公开(公告)号：US07899943B2

公开(公告)日：2011-03-01

申请号：US11933126

申请日：2007-10-31

Applicant: Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US07424496B1

公开(公告)日：2008-09-09

申请号：US10103415

申请日：2002-03-20

Applicant: Ilan Pardo

Inventor： Ilan Pardo

IPC: G06F17/30

CPC classification number: G06F9/30101 ,  G06F9/526 ,  Y10S707/99942 ,  Y10S707/99952 ,  Y10S707/99955

Abstract: Prior to updating a database entry, an update task invalidates a valid indicator (e.g., a bit) associated with the database entry. The update task waits for any other tasks (e.g., user tasks) that are accessing the database entry to complete their processing. In particular, a synchronization register holds a synchronization entry (e.g., a bit) for each user task that is created by a micro controller. The update task sets each synchronization entry of the synchronization register to a first value. As each user task completes its processing, the synchronization entry associated with the user task in the synchronization register is set to a second value (e.g., the synchronization bit is reset). The update task monitors the synchronization register, and, when each synchronization entry has been set to the second value, the update task performs its update of the database entry.

Abstract translation: 在更新数据库条目之前，更新任务使与数据库条目相关联的有效指示符（例如，位）无效。 更新任务等待访问数据库条目以完成其处理的任何其他任务（例如，用户任务）。 特别地，同步寄存器保存由微控制器创建的每个用户任务的同步条目（例如，位）。 更新任务将同步寄存器的每个同步条目设置为第一个值。 当每个用户任务完成其处理时，与同步寄存器中的用户任务相关联的同步条目被设置为第二值（例如，同步位被复位）。 更新任务监视同步寄存器，并且当每个同步条目被设置为第二个值时，更新任务执行数据库条目的更新。

公开(公告)号：US20080196034A1

公开(公告)日：2008-08-14

申请号：US11933143

申请日：2007-10-31

Applicant: Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanaliur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanaliur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

IPC: G06F9/46

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US07245616B1

公开(公告)日：2007-07-17

申请号：US10103436

申请日：2002-03-20

Applicant: Nathan Elnathan ,  Alexander Joffe ,  Ilan Pardo

Inventor： Nathan Elnathan ,  Alexander Joffe ,  Ilan Pardo

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/3072

Abstract: Tasks are dynamically allocated to process packets. In particular, packets of data to be processed are assigned a packet identification. The packet identification includes a lane and a packet sequence number. The term “lane” as used herein refers to a port number and a direction (i.e. ingress or egress), such as Port 3 Egress. A set of resources (e.g., registers and memory buffers) are associated with each lane. The task is allowed to access resources associated with the lane. In some embodiments, a task may change the port that it services and use the resources associated with that port.

Abstract translation: 动态分配任务以处理数据包。 特别地，要处理的数据分组被分配一个分组标识。 分组标识包括通道和分组序列号。 本文所用的术语“通道”是指端口号和方向（即入口或出口），例如端口3出口。 一组资源（例如，寄存器和存储器缓冲器）与每个通道相关联。 该任务被允许访问与该通道相关联的资源。 在一些实施例中，任务可以改变其服务的端口并使用与该端口相关联的资源。

公开(公告)号：US5754839A

公开(公告)日：1998-05-19

申请号：US520066

申请日：1995-08-28

Applicant: Ilan Pardo ,  David Shamir ,  Danny Shterman ,  Itai Katz ,  Edward C. Nelson ,  Mark E. Cummins

Inventor： Ilan Pardo ,  David Shamir ,  Danny Shterman ,  Itai Katz ,  Edward C. Nelson ,  Mark E. Cummins

IPC: G06F9/38 ,  G06F11/36 ,  G06F9/00

CPC classification number: G06F11/3636 ,  G06F9/3842

Abstract: An apparatus and method for implementing watchpoints and breakpoints in a data processing system (110). In one embodiment, a pipelined processor (110) performs each instruction of a program. One or more watchpoints are associated with the instructions. The processor includes a history buffer (50) for storing processor state values at the time when each of the instructions was executed, until a predetermined time. Watchpoint information associated with a particular watchpoint is also stored in the history buffer (50), in association with the processor state values, such that the processor state is changed and the watchpoint is announced at the predetermined time. The watchpoint information may include increment/decrement information for one or more counters (41, 42). Breakpoint information may also be stored in history buffer (50).

Abstract translation: 一种用于在数据处理系统（110）中实现观察点和断点的装置和方法。 在一个实施例中，流水线处理器（110）执行程序的每个指令。 一个或多个观察点与指令相关联。 处理器包括用于在执行每个指令时存储处理器状态值的历史缓冲器（50），直到预定时间。 与特定观察点相关联的观察点信息也与处理器状态值相关联地存储在历史缓冲器（50）中，使得处理器状态改变并且在预定时间通知观察点。 观察点信息可以包括用于一个或多个计数器（41,42）的递增/递减信息。 断点信息也可以存储在历史缓冲器（50）中。

公开(公告)号：US5586279A

公开(公告)日：1996-12-17

申请号：US187885

申请日：1994-01-28

Applicant: Ilan Pardo ,  Yair Libman

Inventor： Ilan Pardo ,  Yair Libman

IPC: G06F11/36 ,  G06F12/08

CPC classification number: G06F11/3636 ,  G06F11/3648

Abstract: A cached processor (2) comprises a cache memory (8') having mode switching means for selecting an address capture mode whereby information, such as data and/or instructions, can be captured and stored in all or part of a cache array (30) of the cache memory in real time. The captured information can at any time be transferred to, and used by, an external debug station, coupled to the cached processor, to observe the executed program flow.

Abstract translation: 缓存处理器（2）包括具有模式切换装置的高速缓冲存储器（8'），该模式切换装置用于选择地址捕获模式，由此诸如数据和/或指令的信息可被捕获并存储在高速缓存阵列的全部或部分（30 ）的缓存内存。 所捕获的信息可以随时被传送到外部调试站，并被耦合到缓存的处理器使用，以便观察所执行的程序流程。