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51.发明授权Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines 有权用于将作业调度到多个硬件加速引擎的动态配置的硬件队列公开(公告)号：US09448846B2
公开(公告)日：2016-09-20
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
摘要翻译： 一种具有多个处理资源的计算机系统，包括用于向多个硬件加速器调度和调度处理作业的子系统，所述子系统还包括作业请求器，用于请求具有有限和变化的延迟的作业以在硬件上执行 加速器 队列控制器，用于管理针对多个硬件加速器的处理作业请求; 以及用于将作业分派到所述多个硬件加速引擎的多个硬件队列，每个队列具有专用的队列入口头部，动态共享具有可配置队列深度限制的队列条目池，以及用于移除所有队列中的一个或多个作业的装置 。
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公开(公告)号：US5964855A
公开(公告)日：1999-10-12
申请号：US826789
申请日：1997-04-07
CPC分类号： G06F13/4081
摘要： Method and system for controlling the state of a system bus during live insertion and removal of a pluggable feature card (FC) by driving control signals, which are transferred over the system bus, to an active signal level, or by driving down level active control signals to a low signal level near ground level. By this mechanism, the system bus becomes immune to signal disturbances and thereby allows pluggable units to be live inserted and removed without causing adverse effects to the system such as a system reset or compromise of data integrity. During live insertion or removal, a Live Insertion Bus Controller (LIBC) acquires access to the system bus through its interface with a System Bus Controller (SBC), after it has been signalled by a live insertion mechanism associated with the FC that the FC is in the process of being live inserted or removed. After system bus access has been acquired by the LIBC and the LIBC has taken over the control of the system bus, it drives a subset of the system bus set of control signals to a state that is immune from insertion/removal signal disturbance. In parallel, the LIBC effects suspension of running timeout and watchdog operations currently being performed by the SBC. When the LIBC is informed that the insertion process has been completed, the SBC again acquires control of the system bus. The same procedural steps are performed in case of removal of an FC.
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公开(公告)号：US20130152099A1
公开(公告)日：2013-06-13
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
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54.发明授权Method and apparatus for concurrent and stateful decompression of multiple compressed data streams 失效用于多个压缩数据流的并发和状态解压缩的方法和装置公开(公告)号：US08244911B2
公开(公告)日：2012-08-14
申请号：US12177440
申请日：2008-07-22
申请人： Brian Mitchell Bass , Giora Biran , Hubertus Franke , Hao Yu
发明人： Brian Mitchell Bass , Giora Biran , Hubertus Franke , Hao Yu
CPC分类号： H04L69/04 , G06F2221/2105 , H04L63/0227
摘要： A method for decompressing multiple data streams includes receiving a packet of data of a compressed data stream, directing the received packet to a selected one of a plurality of decompression functional units within a hardware-based decompression accelerator unit, obtaining decompression state information pertaining to the compressed data stream, and decompressing the received packet using the obtained decompression state information.
摘要翻译： 用于解压缩多个数据流的方法包括：接收压缩数据流的数据分组，将接收的分组引导到基于硬件的解压缩加速器单元内的多个解压缩功能单元中的选定的一个，获得与 压缩数据流，并使用获得的解压缩状态信息对接收的分组进行解压缩。
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公开(公告)号：US06560227B1
公开(公告)日：2003-05-06
申请号：US09027860
申请日：1998-02-23
申请人： Robert William Bartoldus , Brian Mitchell Bass , Timothy Lee Droz , Scott David Nellenbach , Kenneth H. Potter, Jr. , Edward Joel Rovner
发明人： Robert William Bartoldus , Brian Mitchell Bass , Timothy Lee Droz , Scott David Nellenbach , Kenneth H. Potter, Jr. , Edward Joel Rovner
IPC分类号： H04L1256
CPC分类号： H04L49/3009 , H04L49/30 , H04L49/351 , H04L49/354
摘要： A LAN interconnect device includes a plurality of Frame Processing Units (FPUs) for coupling each port of the device to a switch fabric. Each one of the Frame Processing Units includes an input section with input logic which prepares LS Headers and appends each one to a block of the frame as the block is forwarded to the switch fabric. The FPU, also, includes an output section with copy logic for copying and assembling frames to be forwarded to devices connected to the port. The copy decision is based upon the LS Header and configuration information in the port.
摘要翻译： LAN互连设备包括用于将设备的每个端口耦合到交换结构的多个帧处理单元（FPU）。 帧处理单元中的每一个包括具有输入逻辑的输入部分，其中准备LS报头并且随着块被转发到交换结构而将每一个附加到帧的块。 FPU还包括具有复制逻辑的输出部分，用于复制和组合要转发到连接到端口的设备的帧。 复制决定基于端口中的LS头和配置信息。
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公开(公告)号：US07818509B2
公开(公告)日：2010-10-19
申请号：US11930393
申请日：2007-10-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016 , G06F2212/1028 , Y02D10/13
摘要： A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.
摘要翻译： 在多节点对称多处理器系统中使用的高速缓存一致性技术，其将读请求的消息阶段的数量从5减少到4，在大多数情况下消除了读请求的组合响应阶段，从而提高系统性能并减少 整体系统功耗。
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公开(公告)号：US20090113138A1
公开(公告)日：2009-04-30
申请号：US11930393
申请日：2007-10-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016 , G06F2212/1028 , Y02D10/13
摘要： A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.
摘要翻译： 在多节点对称多处理器系统中使用的高速缓存一致性技术，其将读请求的消息阶段的数量从5减少到4，在大多数情况下消除了读请求的组合响应阶段，从而提高系统性能并减少 整体系统功耗。
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公开(公告)号：US5793764A
公开(公告)日：1998-08-11
申请号：US614221
申请日：1996-03-12
CPC分类号： H04L45/742 , H04L49/351 , H04L49/3027 , H04L49/40
摘要： A LAN switching system includes an Address Match Control line which can be set (activated) and is monitored by each port adapter card. If a port adapter card recognizes an address on the switch fabric, the adapter card copies the frame with the address and activates the Address match Control line. The set Address Match Control line causes the remaining port adapter cards to stop searching for a match. If the Address Match Control line is not set, the frame can be copied by all port adapters which are configured to do so.
摘要翻译： LAN交换系统包括地址匹配控制线，可以设置（激活）并由每个端口适配卡监视。 如果端口适配器卡识别交换机结构上的地址，则适配器卡将复制带有该地址的帧，并激活“地址匹配控制”行。 设置的地址匹配控制行使剩余的端口适配器卡停止搜索匹配。 如果未设置地址匹配控制行，则可以通过配置为这样做的所有端口适配器复制该帧。
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59.发明申请Method and Apparatus for Concurrent and Stateful Decompression of Multiple Compressed Data Streams 失效用于多个压缩数据流的并发和有状态解压缩的方法和装置公开(公告)号：US20100020825A1
公开(公告)日：2010-01-28
申请号：US12177440
申请日：2008-07-22
申请人： Brian Mitchell Bass , Giora Biran , Hubertus Franke , Hao Yu
发明人： Brian Mitchell Bass , Giora Biran , Hubertus Franke , Hao Yu
IPC分类号： H04L29/02
CPC分类号： H04L69/04 , G06F2221/2105 , H04L63/0227
摘要： A method for decompressing multiple data streams includes receiving a packet of data of a compressed data stream, directing the received packet to a selected one of a plurality of decompression functional units within a hardware-based decompression accelerator unit, obtaining decompression state information pertaining to the compressed data stream, and decompressing the received packet using the obtained decompression state information.
摘要翻译： 用于解压缩多个数据流的方法包括：接收压缩数据流的数据分组，将接收的分组引导到基于硬件的解压缩加速器单元内的多个解压缩功能单元中的选定的一个，获得与 压缩数据流，并使用获得的解压缩状态信息对接收的分组进行解压缩。
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60.发明授权Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system 失效用于在计算机系统中实现非中断活动插入和移除功能卡的方法和系统
公开(公告)号：US6041375A
公开(公告)日：2000-03-21
申请号：US321688
申请日：1999-05-28
CPC分类号： G06F13/4081
摘要： Method and system for controlling the state of a system bus during live insertion and removal of a pluggable feature card (FC) by driving control signals, which are transferred over the system bus, to an active signal level, or by driving down level active control signals to a low signal level near ground level. By this mechanism, the system bus becomes immune to signal disturbances and thereby allows pluggable units to be live inserted and removed without causing adverse effects to the system such as a system reset or compromise of data integrity. During live insertion or removal, a Live Insertion Bus Controller (LIBC) acquires access to the system bus through its interface with a System Bus Controller (SBC), after it has been signalled by a live insertion mechanism associated with the FC that the FC is in the process of being live inserted or removed. After system bus access has been acquired by the LIBC and the LIBC has taken over the control of the system bus, it drives a subset of the system bus set of control signals to a state that is immune from insertion/removal signal disturbance. In parallel, the LIBC effects suspension of running timeout and watchdog operations currently being performed by the SBC. When the LIBC is informed that the insertion process has been completed, the SBC again acquires control of the system bus. The same procedural steps are performed in case of removal of an FC.
摘要翻译： 用于通过将通过系统总线传送的控制信号驱动到活动信号电平或通过驱动下降电平主动控制来实时插入和移除可插拔特征卡（FC）来控制系统总线的状态的方法和系统 信号到地平面附近的低信号电平。 通过这种机制，系统总线免受信号干扰的影响，从而允许可插拔单元被实时插入和移除，而不会对系统造成不利影响，例如系统复位或泄漏数据完整性。 在实时插入或删除过程中，实时插入总线控制器（LIBC）通过与系统总线控制器（SBC）的接口获取对系统总线的访问，在通过与FC相关的活动插入机制发出信号后，FC为FC 在被插入或移除的过程中。 在LIBC已经获得系统总线访问之后，LIBC已经接管了系统总线的控制，它将系统总线控制信号的一部分驱动到不受插入/移除信号干扰的状态。 同时，LIBC会影响SBC正在执行的运行超时和看门狗操作的暂停。 当LIBC被告知插入过程已经完成时，SBC再次获得对系统总线的控制。 在删除FC的情况下执行相同的程序步骤。
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