利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.031 秒)

    Multiple logical interfaces to a shared coprocessor resource
    6.
    发明授权
    Multiple logical interfaces to a shared coprocessor resource 失效
    到共享协处理器资源的多个逻辑接口

    公开(公告)号：US06829697B1

    公开(公告)日：2004-12-07

    申请号：US09656582

    申请日：2000-09-06

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    IPC分类号： G06F1500

    CPC分类号： G06F15/7864

    摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.

    摘要翻译： 嵌入式处理器复合体包含多个协议处理器单元（PPU）。 每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。 每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。 操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。 指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

    Method and system for frame and protocol classification
    7.
    发明授权
    Method and system for frame and protocol classification 失效
    框架和协议分类的方法和系统

    公开(公告)号：US07440417B2

    公开(公告)日：2008-10-21

    申请号：US10870730

    申请日：2004-06-17

    申请人： Anthony Matteo Gallo ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Michael Steven Siegel ,  Jean Louis Calvignac ,  Gordon Taylor Davis

    发明人： Anthony Matteo Gallo ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Michael Steven Siegel ,  Jean Louis Calvignac ,  Gordon Taylor Davis

    IPC分类号： H04L12/28

    CPC分类号： H04L29/06 ,  H04L69/18 ,  H04L69/22

    摘要： A system and method of protocol and frame classification in a system for data processing is disclosed, including, analyzing a portion of the, packet or frame according to predetermined tests, and storing characteristics of the packet for use in subsequent processing of the frame. The characteristics are preferably obtained with hardware, which does so quickly and in a uniform time period. The stored characteristics of the packet are then used by the network processing complexes in further processing of the frame. The processor is preconditioned with a starting instruction address or cede entry point and the location of the beginning of the layer 3 header as well as flags for the type of frame.

    摘要翻译： 公开了一种用于数据处理的系统中的协议和帧分类的系统和方法，包括：根据预定的测试分析一部分数据包或帧，以及存储该数据包的特性以用于帧的后续处理。 这些特征优选地通过硬件获得，硬件在快速且均匀的时间周期内这样做。 然后，分组的存储特性由网络处理复合体用于帧的进一步处理。 处理器使用开始指令地址或者入门点进行预处理，并且第3层头的开始位置以及帧类型的标志。

    Method and system for frame and protocol classification
    8.
    发明授权
    Method and system for frame and protocol classification 失效
    框架和协议分类的方法和系统

    公开(公告)号：US06775284B1

    公开(公告)日：2004-08-10

    申请号：US09479027

    申请日：2000-01-07

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Michael Steven Siegel

    IPC分类号： H04L1256

    CPC分类号： H04L29/06 ,  H04L69/18 ,  H04L69/22

    摘要： A system and method of protocol and frame classification in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the packet or frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit, such as the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address and flags indicating whether the frame uses a virtual local area network, preferably using hardware to quickly and in a uniform time period. The stored key characteristics of the packet are then used by the network processing complexes in its further processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additionally, additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions.

    摘要翻译： 用于数据处理（例如，切换或路由数据分组或帧）的系统中的协议和帧分类的系统和方法。 本发明包括根据预定的测试来分析分组或帧的一部分，然后存储该分组的关键特征以用于该帧的后续处理。 帧（或输入信息单元，例如帧中使用的层3协议的类型，第2层封装技术，起始指令地址和指示帧是否使用虚拟局域网的标志）的关键特性，优选地使用 硬件在快速和统一的时间段内，存储的密钥特性随后由网络处理复合体在帧的进一步处理中被使用，处理器使用起始指令地址和开始指令的位置进行预处理 第3层标题以及帧类型的标志，即处理器使用指令地址或代码入口点，根据帧类型对正确位置的帧开始处理，另外附加指令 地址可以在分支上顺序堆叠和使用，以避免额外的测试和分支指令。

    Controller for multiple instruction thread processors
    9.
    发明授权
    Controller for multiple instruction thread processors 失效
    多指令线程处理器的控制器

    公开(公告)号：US08006244B2

    公开(公告)日：2011-08-23

    申请号：US10915983

    申请日：2004-08-11

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

    摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。