公开(公告)号：US11429292B2

公开(公告)日：2022-08-30

申请号：US17110197

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F3/06

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

公开(公告)号：US20220130431A1

公开(公告)日：2022-04-28

申请号：US17569303

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F13/16

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US11177007B2

公开(公告)日：2021-11-16

申请号：US16798893

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C5/14 ,  G11C16/30 ,  G06F1/28 ,  G06F1/3296

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

公开(公告)号：US20210264992A1

公开(公告)日：2021-08-26

申请号：US16798893

申请日：2020-02-24

Applicant: Micron Technology, Inc

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C16/30 ,  G06F1/3296 ,  G06F1/28

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

公开(公告)号：US11081161B2

公开(公告)日：2021-08-03

申请号：US16185464

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/14 ,  G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US20210217482A1

公开(公告)日：2021-07-15

申请号：US16740275

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C16/30 ,  G11C5/14

Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

公开(公告)号：US20200258563A1

公开(公告)日：2020-08-13

申请号：US16863967

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US20200152255A1

公开(公告)日：2020-05-14

申请号：US16185464

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US20180158800A1

公开(公告)日：2018-06-07

申请号：US15372246

申请日：2016-12-07

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: H01L25/065 ,  G05F1/10

CPC classification number: H01L25/0657 ,  G05F1/10 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.