公开(公告)号：US11921560B2

公开(公告)日：2024-03-05

申请号：US18084149

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F1/32 ,  G06F1/3225

CPC classification number: G06F1/3225

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

公开(公告)号：US11726541B2

公开(公告)日：2023-08-15

申请号：US17502458

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G06F11/30 ,  G06F1/3225 ,  G06F1/30 ,  G06F1/3293

CPC classification number: G06F1/3225 ,  G06F1/30 ,  G06F1/3293

Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

公开(公告)号：US20230120654A1

公开(公告)日：2023-04-20

申请号：US18084135

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US11568913B2

公开(公告)日：2023-01-31

申请号：US17164738

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US11561597B2

公开(公告)日：2023-01-24

申请号：US17110140

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F1/32 ,  G06F1/3225

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

公开(公告)号：US11353944B2

公开(公告)日：2022-06-07

申请号：US16863968

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Baekkyu Choi ,  Thomas H. Kinsley

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F3/06

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

公开(公告)号：US20220171548A1

公开(公告)日：2022-06-02

申请号：US17110197

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F3/06

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

公开(公告)号：US20210383849A1

公开(公告)日：2021-12-09

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US10796729B2

公开(公告)日：2020-10-06

申请号：US16268092

申请日：2019-02-05

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/22 ,  G11C5/06 ,  G11C11/4091 ,  G06F13/16 ,  G11C11/56 ,  G11C11/408

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US20200310520A1

公开(公告)日：2020-10-01

申请号：US16369804

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Baekkyu Choi ,  Thomas H. Kinsley

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F3/06

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.