公开(公告)号：US20230102577A1

公开(公告)日：2023-03-30

申请号：US18077762

申请日：2022-12-08

Applicant: Micron Technology, Inc.

Inventor： Ying Huang ,  Mark Ish

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.

公开(公告)号：US11579799B2

公开(公告)日：2023-02-14

申请号：US16822916

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Mark Ish ,  Yun Li ,  Scheheresade Virani ,  John Paul Traver ,  Ning Zhao

IPC: G06F3/06 ,  G06F9/50

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

公开(公告)号：US11481348B2

公开(公告)日：2022-10-25

申请号：US17161303

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Lyle E. Adams ,  Mark Ish ,  Pushpa Seetamraju ,  Karl D. Schuh ,  Dan Tupy

IPC: G06F12/14 ,  G06F13/376 ,  G06F13/16 ,  G06F3/06

Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.

公开(公告)号：US20220236920A1

公开(公告)日：2022-07-28

申请号：US17722856

申请日：2022-04-18

Applicant: Micron Technology, Inc.

Inventor： Mark Ish

IPC: G06F3/06 ,  G11C16/26

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.

公开(公告)号：US20220171574A1

公开(公告)日：2022-06-02

申请号：US17675888

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao ,  Steven S. Williams ,  Mark Ish ,  John Edward Maroney

IPC: G06F3/06 ,  G06F12/10

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

公开(公告)号：US11269552B2

公开(公告)日：2022-03-08

申请号：US16866326

申请日：2020-05-04

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao ,  Steven S. Williams ,  Mark Ish ,  John Edward Maroney

IPC: G06F12/10 ,  G06F3/06

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

公开(公告)号：US20210406167A1

公开(公告)日：2021-12-30

申请号：US16914939

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Alexei Frolikov ,  Mark Ish

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0806

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

公开(公告)号：US11113007B2

公开(公告)日：2021-09-07

申请号：US16865248

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao ,  Mark Ish

IPC: G06F3/06

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

公开(公告)号：US20210191850A1

公开(公告)日：2021-06-24

申请号：US16722717

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao ,  Johnny A. Lam ,  John E. Maroney ,  Mark Ish

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0882 ,  G06F9/355

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

公开(公告)号：US10942879B2

公开(公告)日：2021-03-09

申请号：US16886656

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Lyle E. Adams ,  Mark Ish ,  Pushpa Seetamraju ,  Karl D. Schuh ,  Dan Tupy

IPC: G06F12/14 ,  G06F13/376 ,  G06F13/16 ,  G06F3/06

Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.